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Maestro: A high performance AES encryption/decryption system
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Maestro: A high performance AES encryption/decryption system

Biglari, M.

  1. DOI:10.1109/CADS.2013.6714255
  2. Main Entry: Biglari, M.
  3. Title:Maestro: A high performance AES encryption/decryption system.
  4. Publisher:IEEE Computer Society, 2013.
  5. Abstract:High throughput AES encryption/decryption is a necessity for many of modern embedded systems. This article presents a high performance yet cost efficient AES system. Maestro can be used in a wide range of embedded applications with various requirements and limitations. Maestro is about one million times faster than the pure software implementation. The Maestro architecture is composed of two major components; the soft processor aimed at system initialization and control, and the hardware AES engine for high performance AES encryption/decryption. A ten stage implicit pipelined architecture is considered for the AES engine. Two novel techniques are proposed in design of AES engine which enable it to reach a throughput of 12.8 Gbps. First, tightly coupled encryption and round key generation units in encryption unit, and second, ahead of time round key generation in decryption unit. Altera DE2-115 development and educational FPGA board is used as the platform for Maestro. In the proposed architecture the DMA modules act as interfaces between data sources and data sinks by loading the input data into AES engine and taking encrypted and generated test data to target memories
  6. Notes:Sharif Repository
  7. Subject:Advanced Encryption Standard (AES)
  8. Subject:Design Contest.
  9. Subject:FPGA.
  10. Subject:Closed loop control systems.
  11. Subject:Computer architecture.
  12. Subject:Data privacy.
  13. Subject:Engines.
  14. Subject:Field programmable gate arrays (FPGA)
  15. Subject:Throughput.
  16. Subject:Design contests.
  17. Subject:Embedded application.
  18. Subject:FPGASoC.
  19. Subject:Modern embedded systems.
  20. Subject:Pipelined architecture.
  21. Subject:Proposed architectures.
  22. Subject:Software implementation.
  23. Subject:Cryptography.
  24. Added Entry:Qasemi, E.
  25. Added Entry:Pourmohseni, B.
  26. Added Entry:Computer Society of Iran; IPM.
  27. Added Entry:Sharif University of Technology.
  28. Added Entry:CADS 2013
  29. Added Entry:17th CSI International Symposium on Computer Architecture and Digital Systems, CADS 2013, Tehran, Iran, 30 October 2013 through 31 October 2013
  30. Source: Proceedings - 17th CSI International Symposium on Computer Architecture and Digital Systems, CADS 2013 ; October , 2013 , Pages 145-148 ; 9781479905621 (ISBN)
  31. Web Site:http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6714255

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