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Performance evaluation of butterfly on-chip network for MPSoCs
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Performance evaluation of butterfly on-chip network for MPSoCs

Arjomand, M.

  1. DOI:10.1109/SOCDC.2008.4815631
  2. Main Entry: Arjomand, M.
  3. Title:Performance evaluation of butterfly on-chip network for MPSoCs.
  4. Publisher:2008.
  5. Abstract:By Technology improvement, tens or hundreds of IP cores, operating complex functions with different frequencies, are mapped on-chip. This results in heterogeneous Multiprocessor System-on-Chip (MPSoC). The most MPSoC design challenges are due to infrastructure interconnect. Network-on-Chip (NoC) with multiple constraints to be satisfied is a promising solution for these challenges. It has been shown that infrastructure topology, routing and switching schemes have great effects on overall interconnect performance under different synthesis and real life traffic patterns. In this paper, we evaluate Butterfly network with arbitrary extra stages as MPSoC infrastructure. Different routing and switching strategies are used for architectural consideration. Comparative analysis of results with common NoC infrastructures shows that in bandwidth requirement applications, Butterfly with extra stages and wormhole (and sometimes virtual cut through) switching can tolerate traffic, properly. As case studies, design space exploration including different topologies, routing and switching strategies for two video decoders are presented. ©2008 IEEE
  6. Notes:Sharif Repository
  7. Subject:Butterfly network.
  8. Subject:Multiprocessor system-on-chip.
  9. Subject:Network-on-chip.
  10. Subject:Performance aware design.
  11. Subject:Power.
  12. Subject:Simulation modeling.
  13. Subject:Virtual cut through switching.
  14. Subject:Application specific integrated circuits.
  15. Subject:Design.
  16. Subject:Electric network topology.
  17. Subject:Microprocessor chips.
  18. Subject:Multiprocessing systems.
  19. Subject:Programmable logic controllers.
  20. Subject:Space research.
  21. Subject:Switching.
  22. Subject:Topology.
  23. Subject:Computer simulation.
  24. Added Entry:Sarbazi Azad, H.
  25. Added Entry:Sharif University of Technology.
  26. Source: 2008 International SoC Design Conference, ISOCC 2008, Busan, 24 November 2008 through 25 November 2008 ; Volume 1 , 2008 , Pages I296-I299 ; 9781424425990 (ISBN)
  27. Web Site:https://ieeexplore.ieee.org/document/4815631

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