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Digital system test and testable design : using HDL models and architectures
Navabi, Zainalabedin.
- ISBN:1441975470
- ISBN:9781441975478
- ISBN:1441975489
- ISBN:9781441975485
- Call Number : TK 7874 .N38 2011
- Main Entry: Navabi, Zainalabedin.
- Title:Digital system test and testable design : using HDL models and architectures [electronic resource] / Zainalabedin Navabi.
- Publisher:New York : Springer, 2011.
- Physical Description: xxiii, 435 p.: ill. (some col.)
- Notes:CD no.1221
- Notes:Includes bibliographical references and index
- Subject:Digital integrated circuits -- Testing.
- Subject:Digital integrated circuits -- Design and construction.
- Subject:Verilog (Computer hardware description language)
- Reproduction no./Source:978-1-4419-7547-8 Springer http://www.springerlink.com
Digital system test and testable design محتواي کتاب
- Digital System Testand Testable Design
- Preface
- Acknowledgments
- Contents
- Introduction
- Software and Course Materials
- Chapter 1: Basics of Test and Role of HDLs
- Chapter 2: Verilog HDL for Design and Test
- Chapter 3: Fault and Defect Modeling
- 3.1 Fault Modeling
- 3.2 Structural Gate Level Faults
- 3.3 Issues Related to Gate Level Faults
- 3.4 Fault Collapsing
- 3.5 Fault Collapsing in Verilog
- 3.6 Summary
- References
- Chapter 4: Fault Simulation Applications and Methods
- 4.1 Fault Simulation
- 4.2 Fault Simulation Applications
- 4.3 Fault Simulation Technologies
- 4.4 Summary
- References
- Chapter 5: Test Pattern Generation Methods and Algorithms
- 5.1 Test Generation Basics
- 5.2 Controllability and Observability
- 5.3 Random Test Generation
- 5.4 Summary
- References
- Chapter 6: Deterministic Test Generation Algorithms
- 6.1 Deterministic Test Generation Methods
- 6.2 Sequential Circuit Test Generation
- 6.3Test Data Compaction
- 6.4 Summary
- References
- Chapter 7: Design for Test by Means of Scan
- 7.1 Making Circuits Testable
- 7.2 Testability Insertion
- 7.3 Full Scan DFT Technique
- 7.4 Scan Architectures
- 7.5 RT Level Scan Design
- 7.6 Summary
- References
- Chapter 8: Standard IEEE Test Access Methods
- Chapter 9: Logic Built-in Self-test
- 9.1 BIST Basics
- 9.2 Test Pattern Generation
- 9.3 Output Response Analysis
- 9.4 BIST Architectures
- 9.5 RT Level BIST Design
- 9.6 Summary
- References
- Chapter 10: Test Compression
- Chapter 11: Memory Testing by Means of Memory BIST
- Appendix A Using HDLs for Protocol Aware ATE1
- Appendix B Gate Components for PLI Test Applications
- Appendix C Programming Language Interface Test Utilities
- Appendix D IEEE Std. 1149.1 Boundary Scan Verilog Description
- Appendix E Boundary Scan IEEE std. 1149.1 Virtual Tester
- Appendix F Generating Netlist by Register Transfer LevelSynthesis (NetlistGen)
- Index