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  1. ???fa.A 675 Mbps, 4×4 64-qam k-best mimo detector in 0.13 μm CMOS???
A 675 Mbps, 4×4 64-qam k-best mimo detector in 0.13 μm CMOS
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A 675 Mbps, 4×4 64-qam k-best mimo detector in 0.13 μm CMOS

Shabany, M.

  1. DOI:10.1109/TVLSI.2010.2090367
  2. Main Entry: Shabany, M.
  3. Title:A 675 Mbps, 4×4 64-qam k-best mimo detector in 0.13 μm CMOS.
  4. Publisher:2012.
  5. Abstract:This paper introduces a novel scalable pipelined VLSI architecture for a 4×4 64-QAM hard-output multiple-input-multiple-output (MIMO) detector based on K-best lattice decoders. The key contribution is a means of expanding the intermediate nodes of the search tree on-demand, rather than exhaustively, along with three types of distributed sorters operating in a pipelined structure. The proposed architecture has a fixed critical path independent of the constellation size, on-demand expansion scheme, efficient distributed sorters, and is scalable to higher number of antennas. Fabricated in 0.13 μCMOS, it occupies 0.95 μ mm} 2 core area. Operating at 282 MHz clock frequency, it dissipates 135 mW at 1.3 V supply with no BER performance loss. It achieves an SNR-independent throughput of 675 Mbps satisfying the requirements of IEEE 802.16m and long term evolution (LTE) systems. The measurements confirm that this design consumes 3.0×less energy/bit and operates at a significantly higher throughput compared to the best previously published design
  6. Notes:Sharif Repository
  7. Subject:K-best detectors.
  8. Subject:Long term evolution (LTE) systems.
  9. Subject:Multiple-input-multiple-output (MIMO) detection.
  10. Subject:WiMAX systems.
  11. Subject:802.16m.
  12. Subject:BER performance.
  13. Subject:Clock frequency.
  14. Subject:Constellation sizes.
  15. Subject:Core area.
  16. Subject:Critical Paths.
  17. Subject:Intermediate node.
  18. Subject:Lattice decoders.
  19. Subject:Long term evolution.
  20. Subject:MIMO detectors.
  21. Subject:Multiple-input-multiple-output.
  22. Subject:Proposed architectures.
  23. Subject:Search trees.
  24. Subject:VLSI architectures.
  25. Subject:Integrated circuit testing.
  26. Subject:Telecommunication repeaters.
  27. Subject:Wimax.
  28. Subject:Detectors.
  29. Added Entry:Gulak, P. G.
  30. Added Entry:Sharif University of Technology.
  31. Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems ; Volume 20, Issue 1 , December , 2012 , Pages 135-147 ; 10638210 (ISSN)
  32. Web Site:http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=5661890&url=http%3A%2F%2Fieeexplore.ieee.org%2Fxpls%2Fabs_all.jsp%3Farnumber%3D5661890

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