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Programming and customizing the AVR microcontroller
Gadre, Dhananjay V.
اطلاعات کتابشناختی
Programming and customizing the AVR microcontroller
Author :
Gadre, Dhananjay V.
Publisher :
McGraw-Hill,
Pub. Year :
2001
Subjects :
Atmel AVR microcontroller. Programmable controllers.
Call Number :
TJ 223 .P76 .G33 2000
جستجو در محتوا
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امتياز صفحه
فهرست مطالب
Practical Microcontroller Engineering with ARM® Technology
(1)
Contents
(9)
Preface
(31)
Acknowledgments
(33)
Trademarks and Copyrights
(35)
Copyright Permissions
(37)
About the Companion Website
(41)
1: Introduction to Microcontrollers and This Book
(43)
1.1 Microcontroller Configuration and Structure
(44)
1.2 The Arm® Cortex®M4 Microcontroller System
(45)
1.3 The Tm4c123gh6pm Microcontroller Development Tools and Kits
(46)
1.4 Outstanding Features About This Book
(47)
1.5 Who This Book Is For
(47)
1.6 What This Book Covers
(48)
1.7 How This Book Is Organized and How to Use This Book
(50)
1.8 How to Use the Source Code and Sample Projects
(51)
1.9 Instructors and Customers Supports
(53)
2: ARM® Microcontroller Architectures
(55)
2.1 Overview and Introduction
(55)
2.2 Introduction to Arm® Cortex®-M4 Mcu
(57)
2.2.1 The Architecture of ARM® Cortex®-M4 MCU
(59)
2.2.1.1 The ARM® MCU Architecture
(59)
2.2.1.2 The Architecture of the ARM® Cortex®-M4 Core (CPU)
(62)
2.2.1.2.1 The Register Bank in the Cortex®-M4 Core
(63)
2.2.1.2.2 The Special Registers in the Cortex®-M4 Core
(64)
2.2.1.3 The Architecture of the Floating-Point Registers
(67)
2.3 The Memory Architecture
(69)
2.3.1 The Memory Map
(70)
2.3.2 The Stack Memory
(71)
2.3.3 The Program Models and States
(74)
2.3.4 The Memory Protection Unit (MPU)
(75)
2.4 The Nested Vectored Interrupt Controller (Nvic) Architecture
(76)
2.4.1 The Nested Vectored Interrupt Controller (NVIC) Features
(77)
2.4.2 Exception and Interrupt Sources
(77)
2.4.3 Exception Priority Levels and Mask Registers
(77)
2.4.4 Respond and Process Exceptions and Interrupts
(78)
2.4.5 Exception and Interrupt Vector Table
(79)
2.5 The Debug Architecture
(79)
2.6 Introduction to Tiva™ C Series Arm® Cortex®-M4 Mcu - Tm4c123gh6pm
(80)
2.6.1 TM4C123GH6PM Microcontroller Overview
(81)
2.6.2 TM4C123GH6PM Microcontroller On-Chip Memory Map
(82)
2.6.2.1 The System Peripherals
(84)
2.6.2.2 The On-Chip Peripherals
(84)
2.6.2.3 Interfaces to External Parallel Peripherals
(86)
2.6.2.4 Interfaces to External Serial Peripherals
(86)
2.6.3 TM4C123GH6PM Microcontroller General-Purpose Input-Output (GPIO) Module
(86)
2.6.3.1 The System Clock
(87)
2.6.3.2 The General Configuration Procedures for GPIO Peripherals
(89)
2.6.3.3 Tiva™ TM4C123GH6PM GPIO Architecture
(89)
2.6.3.3.1 The Port Control Register (GPIOPCTL)
(91)
2.6.3.3.2 The Data Control Registers
(91)
2.6.3.3.3 The Mode Control Registers
(91)
2.6.3.3.4 The Commit Control Registers
(93)
2.6.3.3.5 The Interrupt Control Registers
(93)
2.6.3.3.6 The Pad Control Registers
(94)
2.6.3.3.7 The Identification Registers
(97)
2.6.3.4 The Initialization and Configuration of TM4C123GH6PM GPIO Ports
(97)
2.6.4 TM4C123GH6PM Microcontroller System Controls
(99)
2.6.4.1 Device Identification
(100)
2.6.4.2 Reset Control
(101)
2.6.4.2.1 The Power-On Reset
(102)
2.6.4.2.2 The External Reset
(103)
2.6.4.2.3 The Brown-Out Reset (BOR)
(103)
2.6.4.2.4 The Software Reset
(103)
2.6.4.2.5 The Watchdog Timer Reset
(104)
2.6.4.3 Non-Maskable Interrupt Control
(105)
2.6.4.4 Clock Control
(106)
2.6.4.5 Other System Controls
(109)
2.6.4.5.1 The Run Mode
(109)
2.6.4.5.2 The Sleep Mode
(110)
2.6.4.5.3 The Deep-Sleep Mode
(110)
2.6.4.5.4 The Hibernate Mode
(110)
2.6.4.5.5 The System Timer (SysTick)
(111)
2.6.4.5.6 System Control Block (SCB)
(112)
2.6.4.6 System Clock Initialization and Configuration
(113)
2.7 Introduction to Tiva™ C Series Launchpad™ Tm4c123gxl Evaluation Board
(114)
2.8 Introduction to Edubase Arm® Trainer
(119)
2.9 Chapter Summary
(119)
Homework
(121)
3: ARM® Microcontroller Development Kits
(125)
3.1 Overview and Introduction
(125)
3.2 The Entire Tiva™ Tm4c123g-Based Development System
(126)
3.3 Download and Install Development Suite and Specified Firmware
(128)
3.4 Introduction to the Integrated Development Environment-Keil® Mdk Μversion5
(129)
3.4.1 The Keil® MDK-ARM® for the MDK-Cortex-M Family
(130)
3.4.2 General Development Flow with MDK-ARM®
(131)
3.4.3 Warming Up Keil® MDK Cortex-M Kit with Example Projects
(133)
3.4.4 The Functions of the Keil® MDK-ARM® μVersion®5 GUI
(137)
3.4.4.1 The File Menu
(139)
3.4.4.2 The Edit Menu
(140)
3.4.4.3 The Project Menu
(143)
3.4.4.4 The Flash Menu
(163)
3.4.4.5 The Debug Menu
(163)
3.4.4.6 The Peripherals Menu
(165)
3.4.4.7 The Tools Menu
(166)
3.4.4.8 The SVCS Menu
(167)
3.4.4.9 The Window Menu
(168)
3.4.4.10 The Help Menu
(168)
3.5 Embedded Software Development Procedure
(169)
3.6 The Keil® Arm®-Mdk μvision5 Debugger and Debug Process
(170)
3.6.1 The ARM® μVision5 Debug Architecture
(171)
3.6.2 The ARM® Debug Adaptor and Debug Adaptor Driver
(172)
3.6.3 Tiva™ C Series LaunchPad™ Debug Adaptor and Debug Adaptor Driver
(174)
3.6.4 The ARM® μVersion5 Debug Process
(175)
3.6.5 The ARM® Trace Feature
(176)
3.6.5.1 Some Useful Trace Features Provided by Cortex®-M4 MCU
(177)
3.6.6 The ARM® Instruction Set Simulator
(178)
3.6.7 The ARM® Programs Running from SRAM
(179)
3.6.8 ARM® Optimizations
(181)
3.7 The Tivaware™ for C Series Software Suite
(182)
3.7.1 The TivaWare™ C Series Software Package
(184)
3.7.1.1 The Peripheral Driver Library (DriverLib)
(185)
3.7.1.2 The Boot Loader
(186)
3.7.1.3 The Utilities
(186)
3.7.2 TivaWare™ C Series for TM4C123G LaunchPad™ Evaluation Kit
(187)
3.7.2.1 TivaWare™ C Series LaunchPad™ Evaluation Software Package
(187)
3.8 The Tivaware™ for C Series Utilities and Other Supports
(189)
3.8.1 Additional Utilities Provided by TivaWare™ for C Series
(190)
3.8.1.1 The LMFlash Programmer
(190)
3.8.1.2 The UniFlash
(191)
3.8.1.3 The FTDI Drivers
(191)
3.8.1.4 The IQMath Library
(191)
3.8.1.5 TivaWare™ for C Series CMSIS Support
(192)
3.9 Program Examples
(193)
3.10 Chapter Summary
(194)
Homework
(194)
4: ARM® Microcontroller Software and Instruction Set
(197)
4.1 Overview and Introduction
(197)
4.2 Introduction to Arm® Cortex®-M4 Software Development Structure
(198)
4.3 Introduction to Arm® Cortex®-M4 Assembly Instruction Set
(199)
4.3.1 The ARM® Cortex®-M4 Assembly Language Syntax
(200)
4.3.2 The ARM® Cortex®-M4 Pseudo Instructions
(202)
4.3.3 The ARM® Cortex®-M4 Addressing Modes
(203)
4.3.3.1 The Immediate Offset Addressing Mode
(204)
4.3.3.1.1 Regular Immediate Offset Addressing Mode
(204)
4.3.3.1.2 Pre-Indexed Immediate Offset Addressing Mode
(205)
4.3.3.1.3 Post-Indexed Immediate Offset Addressing Mode
(205)
4.3.3.1.4 Regular Immediate Offset Addressing Mode with Unprivileged Access
(205)
4.3.3.2 The Register Offset Addressing Mode
(206)
4.3.3.3 The PC-Relative Addressing Mode
(207)
4.3.3.4 Load and Store Multiple Registers Addressing Mode
(209)
4.3.3.5 PUSH and POP Register Addressing Mode
(212)
4.3.3.6 Load and Store Register Exclusive Addressing Mode
(212)
4.3.3.7 Inherent Addressing Mode
(213)
4.3.3.8 Addressing Mode Summary
(213)
4.3.4 The ARM® Cortex®-M4 Instruction Set Categories
(214)
4.3.4.1 Data Moving Instructions
(214)
4.3.4.2 Arithmetic Instructions
(216)
4.3.4.3 Logic Instructions
(218)
4.3.4.4 Shift and Rotate Instructions
(220)
4.3.4.5 Data Conversion Instructions
(221)
4.3.4.6 Bit-Field Processing Instructions
(224)
4.3.4.7 Compare and Test Instructions
(228)
4.3.4.8 Program Flow Control Instructions
(229)
4.3.4.9 Saturation Instructions
(233)
4.3.4.10 Exception-Related Instructions
(235)
4.3.4.11 Sleep Mode Instructions
(236)
4.3.4.12 Memory Barrier Instructions
(236)
4.3.4.13 Miscellaneous Instructions
(237)
4.3.4.14 Unsupported Instructions
(238)
4.4 Arm® Cortex®-M4 Software Development Procedures
(238)
4.5 Using C Language to Develop Arm® Cortex®-M4 Microcontroller Applications
(239)
4.5.1 The Standard Data Types Used in Intrinsic Functions
(240)
4.5.2 The CMSIS-Core-Specific Intrinsic Functions
(242)
4.5.3 The Keil® ARM® Compiler-Specific Intrinsic Functions
(244)
4.5.4 Inline Assembler
(246)
4.5.5 Idiom Recognition
(247)
4.5.6 C Programming Development Guideline and Procedure
(248)
4.5.6.1 Organization of the C Program Files
(249)
4.5.6.2 The Header Files
(250)
4.5.6.3 The Implementation Files
(251)
4.5.6.4 The Application Files
(253)
4.5.6.5 Naming Convention and Definition
(253)
4.5.7 The TivaWare™ Peripheral Driver Library
(255)
4.5.7.1 The Programming Models
(255)
4.5.7.2 The Direct Register Access Model
(256)
4.5.7.2.1 The Hardware Architecture of the Example Project
(256)
4.5.7.2.2 The Structure and Bit Function of System Control and GPIO Registers
(257)
4.5.7.2.3 The Symbolic Definitions and Macros
(260)
4.5.7.2.4 The Programming Operations for Symbolic Definitions
(261)
4.5.7.2.5 Develop a Sample Project Using the DRA Model
(262)
4.5.7.3 The Peripheral Driver Library and API Functions
(266)
4.5.7.3.1 System Control API Functions
(267)
4.5.7.3.2 GPIO API Functions
(271)
4.5.7.3.3 Develop a Sample Project Using the SD Model
(274)
4.5.7.4 A Comparison Between Two Programming Models
(280)
4.5.7.5 A Combined Programming Model Example
(280)
4.5.7.5.1 Create the Header File
(281)
4.5.7.5.2 Create the C Source File
(282)
4.5.7.5.3 Include System Header Files and Add Static Library into the Project
(283)
4.5.7.5.4 Compile and Link Project to Create the Image or Executable File
(284)
4.6 Chapter Summary
(285)
Homework
(286)
5: ARM® Microcontroller Interrupts and Exceptions
(303)
5.1 Overview and Introduction
(303)
5.2 Exceptions and Interrupts in the Arm® Cortex®-M4 Mcu System
(305)
5.2.1 Exception and Interrupt Types
(307)
5.2.2 Exceptions and Interrupts Management
(307)
5.2.3 Exception and Interrupt Processing
(310)
5.2.3.1 Exception and Interrupt Inputs and Pending Status
(311)
5.2.3.2 Exception and Interrupt Vector Table
(312)
5.2.3.3 Definitions of the Priority Levels
(313)
5.3 Exceptions and Interrupts in the Tm4c123gh6pm Microcontroller System
(315)
5.3.1 Local Interrupt Configurations and Controls for GPIO Pins
(315)
5.3.1.1 Initialize and Configure GPIO Interrupt Control Registers
(316)
5.3.2 Local Interrupt Configurations and Controls for GPIO Ports
(318)
5.3.2.1 The NVIC Interrupt Priority-Level Registers
(318)
5.3.2.2 The NVIC Interrupt Set Enable Registers
(322)
5.3.3 Global Interrupt Configurations and Controls
(323)
5.3.4 The Vector Table and Vectors Used in the TM4C123GH6PM MCU
(324)
5.3.5 The GPIO Interrupt Handling and Processing Procedure
(326)
5.4 Developing Gpio Port Interrupt Projects to Handle Gpio Interrupts
(327)
5.4.1 Two Software Packages Used in the TM4C123GH6PM MCU System
(328)
5.4.1.1 The TivaWare™ Software Package (TWSP)
(328)
5.4.1.1.1 Two Header Files Used in the TM4C123GH6PM MCU System
(330)
5.4.1.1.2 The Register Driver Definition Header File in the TivaWare™ Software Package
(331)
5.4.1.1.3 The CMSIS Cortex-M4 Peripheral Layer Header File for TM4C123GH6PM
(331)
5.4.1.2 The CMSIS Core Software Package (CMSISCSP)
(332)
5.4.2 Using DRA Programming Model to Handle GPIO Interrupts
(332)
5.4.2.1 Create a New Project GPIOInt and the Header File
(333)
5.4.2.2 Create a New C Code File GPIOInt and Add It into the Project
(334)
5.4.2.3 Set Up the Environment to Compile and Link the Project
(336)
5.4.3 Using CMSIS Core Macros for NVIC Registers to Handle GPIO Interrupts
(336)
5.4.3.1 Popular Data Structures Defined in the CMSIS Core Header File
(337)
5.4.3.2 IRQ Numbers Defined in the TivaWare™ System Header File
(339)
5.4.3.3 The NVIC Macros Defined in the TivaWare™ System Header Files
(341)
5.4.3.4 The NVIC Structure Defined in the CMSIS Core Header File
(342)
5.4.3.5 Building Sample Project to Use CMSIS Core Macros for NVIC to Handle Interrupts
(344)
5.4.3.6 Create a New Project NVICInt and Add the C Code File
(345)
5.4.4 Using TivaWare™ Peripheral Driver Library API Functions to Handle GPIO Interrupts
(348)
5.4.4.1 NVIC API Functions Defined in the TivaWare™ Peripheral Driver Library
(348)
5.4.4.2 GPIO Interrupt-Related API Functions in the TivaWare™ Peripheral Driver Library
(350)
5.4.4.3 Building Sample Project to Use Peripheral Driver Library to Handle Interrupts
(351)
5.4.4.4 Create a New Project SDInt and Add the C Code File
(352)
5.4.4.5 Configuring the Environments and Run the Project
(354)
5.4.5 Using CMSIS Core Access Functions to Handle GPIO Interrupts
(355)
5.4.5.1 Building Sample Project to Use CMSIS Core Functions to Handle Interrupts
(356)
5.4.5.2 Create a New Project CMSISInt and Add the C Code File
(356)
5.4.5.3 Configure the Environments and Run the Project
(358)
5.5 Comparison Among Four Interrupt Programming Methods
(359)
5.6 Chapter Summary
(360)
Homework
(361)
6: ARM® Microcontroller Memory System
(375)
6.1 Overview and Introduction
(375)
6.2 Memory Architecture in the Tm4c123gh6pm Mcu System
(376)
6.2.1 Static Random Access Memory (SRAM)
(378)
6.2.2 Flash Memory
(378)
6.2.2.1 Basic Operations of the Flash Memory
(379)
6.2.2.2 The 32-Word Flash Memory Write Buffer
(380)
6.2.2.3 Flash Control Registers
(381)
6.2.2.4 Boot Configuration Register (BOOTCFG)
(381)
6.2.2.5 Flash Memory Address Register (FMA)
(383)
6.2.2.6 Flash Memory Data Register (FMD)
(384)
6.2.2.7 Flash Memory Control Register (FMC)
(384)
6.2.2.8 Flash Memory Control 2 Register (FMC2)
(384)
6.2.2.9 The Flash Write Buffer Valid Register (FWBVAL)
(385)
6.2.2.10 Flash Controller Raw Interrupt Status Register (FCRIS)
(386)
6.2.2.11 Flash Controller Interrupt Mask Register (FCIM)
(388)
6.2.2.12 Flash Controller Masked Interrupt Status and Clear Register (FCMISC)
(388)
6.2.2.13 Other Control Registers Related to Flash Memory Control
(391)
6.2.3 Flash Memory Protection Control
(391)
6.2.4 Internal Read-Only Memory (ROM)
(393)
6.2.4.1 The Boot Loader
(394)
6.2.4.2 The TivaWare™ Peripheral Driver Library
(394)
6.2.4.3 The ROM Control Register (RMCTL)
(396)
6.2.4.4 The ROM Software Map Register (ROMSWMAP)
(396)
6.2.5 Electrical Erased Programmable Read-Only Memory (EEPROM)
(396)
6.2.5.1 EEPROM Initialization and Configuration
(398)
6.2.5.2 Most Important Control Registers Used in the EEPROM Module
(399)
6.2.5.2.1 The EEPROM Current Block Register (EEBLOCK)
(399)
6.2.5.2.2 The EEPROM Current Offset Register (EEOFFSET)
(399)
6.2.5.2.3 EEPROM Done Status Register (EEDONE)
(399)
6.2.5.2.4 EEPROM Support Control and Status Register (EESUPP)
(401)
6.2.5.2.5 EEPROM Protection Register (EEPROT)
(401)
6.2.5.3 Other Important Control Registers Used in the EEPROM Module
(402)
6.3 Memory Map in Tm4c123gh6pm Mcu System
(403)
6.4 Bit-Band Operations
(404)
6.4.1 The Mapping Relationship Between the Bit-Band Region and the Bit-Band Alias Region
(407)
6.4.2 The Advantages of Using the Bit-Band Operations
(407)
6.4.3 An Illustration Example of Using Bit-Band Alias Addresses
(409)
6.4.4 Bit-Band Operations for Different Data Sizes
(411)
6.4.5 Bit-Band Operations Built in C Programs
(411)
6.5 Memory Requirements and Memory Properties
(412)
6.5.1 Memory Requirements
(413)
6.5.2 Memory Access Attributes
(414)
6.5.3 Memory Endianness
(415)
6.5.3.1 The Little Endian Format
(416)
6.5.3.2 The Big Endian Format
(416)
6.6 Memory System Programming Methods
(417)
6.6.1 The API Functions Used for Flash Memory Programming
(418)
6.6.2 The API Functions Used for EEPROM Programming
(420)
6.7 Memory System Programming Projects
(422)
6.7.1 Flash Memory Programming
(422)
6.7.1.1 Programming Flash Memory for Multiple Words with DRA Method (Polled)
(422)
6.7.1.1.1 The Operational Sequence of the Programming Flash Memory
(422)
6.7.1.1.2 The Programming Macros for Flash Memory Registers and Parameters
(423)
6.7.1.1.3 Build the Project to Program Multiple Words for Flash Memory
(424)
6.7.1.1.4 Build and Run the Project to Perform Erase and Write Operations
(428)
6.7.1.2 Programming Flash Memory for Multiple Words with the DRA Method (Interrupt Driven)
(430)
6.7.1.2.1 The Erase and Write Interrupts Processing Procedure
(431)
6.7.1.2.2 Special Features Utilized in the Project
(432)
6.7.1.2.3 Build the Project to Program Multiple Words for Flash Memory with Interrupts
(432)
6.7.1.2.4 Set Up the Environment to Build and Run the Project
(438)
6.7.1.3 Programming Flash Memory for Buffered Words with the DRA Method
(439)
6.7.1.3.1 The Buffer Words Programming Procedure
(439)
6.7.1.3.2 Develop the Buffer Words Programming Project DRAFlashBuffer
(440)
6.7.1.3.3 Build and Set Up the Environment to Run the Project
(442)
6.7.2 EEPROM Programming
(443)
6.7.2.1 Special Features in the EEPROM Programming Process
(443)
6.7.2.2 EEPROM Programming Operational Sequence
(444)
6.7.2.2.1 Configure and Set Up EEBLOCK and EEOFFSET Registers
(445)
6.7.2.2.2 Implement and Update the EEBLOCK and EEOFFSET Registers
(446)
6.7.3 Three Kinds of System Header Files in TM4C123GH6PM MCU System
(447)
6.7.3.1 The Register Driver Definitions Header File tm4c123gh6pm.h
(447)
6.7.3.2 The CMSIS Cortex®-M4 Peripheral Hardware Layer Header File TM4C123GH6PM.h
(448)
6.7.3.3 System Header Files for All Internal Peripherals and System Control Devices
(448)
6.7.3.4 Enable the EEPROM Module in Run Mode and Reset EEPROM
(449)
6.7.4 Build Example EEPROM Programming Projects
(450)
6.7.4.1 Programming EEPROM with the DRA Method (Polling-Driven)
(450)
6.7.4.1.1 Create the Header File DRAEEPROMPoll.h
(450)
6.7.4.1.2 Create the Source File DRAEEPROMPoll.c
(451)
6.7.4.1.3 Set Up the Environment to Build and Run the Project
(455)
6.7.4.2 Programming EEPROM with the DRA Method (Interrupt-Driven)
(456)
6.7.4.2.1 Modify the Header File DRAEEPROMInt.h
(458)
6.7.4.2.2 Modify the Source File DRAEEPROMInt.c
(459)
6.7.4.2.3 Set Up the Environment to Build and Run the Project
(461)
6.8 Chapter Summary
(462)
Homework
(463)
7: ARM® Cortex®-M4 Parallel I/O Ports Programming
(475)
7.1 Overview and Introduction
(475)
7.2 Gpio Module Architecture and Gpio Port Configuration
(476)
7.3 Gpio Port Control Registers
(479)
7.3.1 GPIO Port Initialization and Configuration
(480)
7.4 On-Board Keypad Interface Programming Project
(482)
7.4.1 The Keypad Interfacing Programming Structure
(483)
7.4.2 Create the Keypad Interfacing Programming Project (Polling-Driven)
(484)
7.4.2.1 Create the C Source File DRAKeyPadPoll.c
(485)
7.4.3 Set Up the Environment to Build and Run the Project
(488)
7.5 Analog-To-Digital Converter Programming Project
(488)
7.5.1 ADC Modules in the TM4C123GH6PM MCU System
(488)
7.5.2 ADC Module Architecture and Functional Block Diagram
(489)
7.5.3 ADC Module Components and Signal Descriptions
(490)
7.5.3.1 Analog Input Signals and GPIO Analog Control Registers
(491)
7.5.3.1.1 GPIO Alternate Function Select (GPIOAFSEL) Register
(492)
7.5.3.1.2 GPIO Digital Enable (GPIODEN) Register
(492)
7.5.3.1.3 GPIO Analog Mode Select (GPIOAMSEL) Register
(493)
7.5.3.2 Sample Sequencer Controls and Their Control Registers
(493)
7.5.3.2.1 ADC Sample Sequencer Input Multiplexer Select (ADCSSMUXn) Register
(494)
7.5.3.2.2 ADC Sample Sequencer Control (ADCSSCTLn) Register
(496)
7.5.3.2.3 ADC Active Sample Sequencer (ADCACTSS) Register
(500)
7.5.3.2.4 ADC Processor Sample Sequencer Initiate (ADCPSSI) Register
(501)
7.5.3.2.5 ADC Sample Sequencer Result FIFO (ADCSSFIFOn) Register
(502)
7.5.3.3 ADC Module Control Functions and Related Registers
(503)
7.5.3.3.1 ADC Module Clocking
(503)
7.5.3.3.2 ADC Interrupt Request and Handling
(505)
7.5.3.3.3 Sampling Events and Trigger Sources
(509)
7.5.3.3.4 DMA Operations
(512)
7.5.4 Analog-to-Digital Converter
(512)
7.5.4.1 Voltage Reference and Resolutions
(513)
7.5.4.2 Differential Input Mode
(513)
7.5.4.3 Internal Temperature Sensor
(514)
7.5.5 Initialization and Configuration
(515)
7.5.5.1 ADC-Related GPIO Ports Initialization
(515)
7.5.5.2 ADC Module Initialization
(516)
7.5.5.3 Sample Sequencers Initialization
(516)
7.5.6 Build the Analog-to-Digital Converter Programming Project
(517)
7.5.6.1 ADC Module in EduBASE ARM® Trainer
(517)
7.5.6.2 Create the ADC Programming Project (Polling-Driven)
(518)
7.5.6.3 Create the Source File DRAADCPoll.c
(518)
7.5.6.4 Set Up the Environment to Build and Run the Project
(521)
7.5.7 ADC Module API Functions Provided in the TivaWare™ Peripheral Driver Library
(522)
7.5.7.1 Configuring and Handling the Sample Sequencers API Functions
(523)
7.5.7.2 Configuring and Controlling the Processor Trigger API Functions
(523)
7.5.7.3 Configuring and Processing the ADC Interrupt API Functions
(525)
7.5.7.4 Build an Example ADC Project Using API Functions
(526)
7.6 Pwm-Controlled Dc and Step Motors Programming Project
(528)
7.6.1 The PWM Principle and Implementations
(529)
7.6.2 PWM Modules in the TM4C123GH6PM MCU System
(529)
7.6.2.1 The PWM Generator Block
(530)
7.6.2.1.1 The PWM Counter (Timer)
(530)
7.6.2.1.2 The PWM Comparators
(530)
7.6.2.1.3 The PWM Output Signals Generator
(531)
7.6.2.1.4 The Dead-Band Generator
(532)
7.6.3 PWM Generator Functional Block Diagram
(532)
7.6.3.1 PWM Generator Block Control Register (PWMnCTL)
(533)
7.6.3.2 PWM Generator Block Load Register (PWMnLOAD)
(535)
7.6.3.3 PWM Generator Block Count Register (PWMnCOUNT)
(535)
7.6.3.4 PWM Generator Block Comparator A Register (PWMnCMPA)
(535)
7.6.3.5 PWM Generator Block Comparator B Register (PWMnCMPB)
(536)
7.6.3.6 PWM Generator A Register (PWMnGENA)
(536)
7.6.3.7 PWM Generator B Register (PWMnGENB)
(537)
7.6.3.8 PWM Generator Dead-Band Control Register (PWMnDBCTL)
(538)
7.6.3.9 PWM Generator Dead-Band Rising-Edge Delay Register (PWMnDBRISE)
(539)
7.6.3.10 PWM Generator Dead-Band Falling-Edge Delay Register (PWMnDBFALL)
(539)
7.6.3.11 PWM Interrupt and Trigger Enable Register (PWMnINTEN)
(540)
7.6.3.12 PWM Raw Interrupt Status Register (PWMnRIS)
(540)
7.6.3.13 PWM Interrupt Status and Clear Register (PWMnISC)
(541)
7.6.3.14 PWM Fault Source n Register (PWMFLTSRCn)
(543)
7.6.4 PWM Module Architecture and Functional Block Diagram
(544)
7.6.4.1 The Control and Status Block
(545)
7.6.4.1.1 The Run-Mode Clock Configuration Register (RCC)
(546)
7.6.4.1.2 The PWM Master Control Register (PWMCTL)
(546)
7.6.4.1.3 The PWM Timer Base Synchronous Register (PWMSYNC)
(546)
7.6.4.1.4 The PWM Status Register (PWMSTATUS)
(547)
7.6.4.1.5 The PWM Peripheral Properties Register (PWMPP)
(547)
7.6.4.2 The Output Control Block
(547)
7.6.4.2.1 The PWM Output Enable Register (PWMENABLE)
(547)
7.6.4.2.2 The PWM Output Inversion Register (PWMINVERT)
(548)
7.6.4.2.3 The PWM Output Fault Register (PWMFAULT)
(548)
7.6.4.2.4 The PWM Fault Condition Value Register (PWMFAULTVAL)
(549)
7.6.4.2.5 The PWM Enable Update Register (PWMENUPD)
(549)
7.6.4.3 The Interrupt Control Block
(549)
7.6.4.3.1 The PWM Interrupt Enable Register (PWMINTEN)
(550)
7.6.4.3.2 The PWM Raw Interrupt Status Register (PWMRIS)
(551)
7.6.4.3.3 The PWM Interrupt Status and Clear Register (PWMISC)
(551)
7.6.5 PWM Module Components and Signal Descriptions
(551)
7.6.5.1 PWM Signal Description
(552)
7.6.5.2 Synchronization Methods
(553)
7.6.5.3 Fault Conditions
(554)
7.6.6 PWM Module Initialization and Configuration
(555)
7.6.6.1 Initialize and Configure the Clock Source for PWM Module and GPIO Ports
(555)
7.6.6.2 Initialize and Configure GPIO Ports and Pins Related to PWM Modules
(555)
7.6.6.3 Initialize and Configure the PWM Module and Generators
(556)
7.6.7 PWM Module Architecture in the EduBASE ARM® Trainer
(557)
7.6.8 Build an Example PWM Programming Project
(558)
7.6.8.1 Create a PWM Application Project DRAPWM
(559)
7.6.8.2 Set Up the Environment to Build and Run the Project
(562)
7.7 The Pwm Api Functions in the Tivaware™ Peripheral Driver Library
(563)
7.7.1 PWM Modules and Generators Configuration and Set Up Control Functions
(563)
7.7.2 PWM Output Control Functions
(565)
7.7.3 PWM Interrupt and Fault Control Functions
(565)
7.8 Chapter Summary
(567)
Homework
(569)
8: ARM® Cortex®-M4 Serial I/O Ports Programming
(589)
8.1 Overview and Introduction
(589)
8.2 Gpio Module Architecture and Gpio Port Configuration
(590)
8.3 Synchronous Serial Interface (Ssi)
(593)
8.3.1 Asynchronous and Synchronous Communication Protocols and Data Framing
(594)
8.3.2 Synchronous Serial Interface Architecture and Functional Block Diagram
(597)
8.3.3 The Synchronous Data Transmission Format and Frame
(598)
8.3.3.1 Texas Instruments™ Synchronous Serial Frame
(600)
8.3.3.2 Freescale SPI Frame
(600)
8.3.3.3 MICROWIRE Frame
(601)
8.3.4 SSI Module Components and Signal Descriptions
(602)
8.3.4.1 SSI Control Signals and GPIO SSI Control Registers
(602)
8.3.4.2 SSI Module Bit Rate Generation and Clock Control
(604)
8.3.4.3 SSI Module Control/Status and FIFO Control
(606)
8.3.4.3.1 SSI Control 1 Register (SSICR1)
(606)
8.3.4.3.2 SSI Status Register (SSISR)
(607)
8.3.4.3.3 SSI Data Register (SSIDR)
(607)
8.3.4.3.4 FIFO Operations
(608)
8.3.4.4 SSI Module Interrupt and DMA Control
(609)
8.3.4.4.1 SSI Interrupt Mask Register (SSIIM)
(610)
8.3.4.4.2 SSI Raw Interrupt Status Register (SSIRIS)
(611)
8.3.4.4.3 SSI DMA Control Register (SSIDMACTL)
(611)
8.3.4.5 SSI Module Transmit/Receive Logic Control
(612)
8.3.4.6 SSI Modules Initialization and Configurations
(612)
8.3.4.6.1 SSI-Module-Related GPIO Ports Initialization
(612)
8.3.4.6.2 SSI Module Initialization and Configuration
(613)
8.3.4.6.3 SSI Module Clock Source and Bit Rate Initialization and Configuration
(613)
8.3.5 Build the On-Board LCD Interface Programming Project
(614)
8.3.5.1 SSI Module Interface for the LCD in EduBASE ARM® Trainer
(614)
8.3.5.2 The Serial Shift Register 74VHCT595
(615)
8.3.5.3 The LCD Module TC1602A and LCD Controller SPLC780
(616)
8.3.5.3.1 Interfacing Control Signals Between the MCU and the SPLC780
(618)
8.3.5.3.2 Control and Interface Programming for SPLC780
(620)
8.3.5.3.3 LCD Programming Instruction Structure and Sequence
(622)
8.3.5.4 Build the Example LCD Interfacing Project
(625)
8.3.5.4.1 Create a Direct Register Access LCD Project DRALCD
(626)
8.3.5.4.2 Create the Header File DRALCD.h
(626)
8.3.5.4.3 Create the C Source File DRALCD.c
(627)
8.3.5.4.4 Set Up the Environment to Build and Run the Project
(631)
8.3.6 Build On-Board 7-Segment LED Interface Programming Project
(631)
8.3.6.1 Structure of 7-Segment LEDs
(631)
8.3.6.2 SSI Module Interface for the 7-Segment LED in the EduBASE ARM® Trainer
(632)
8.3.6.3 Build the Example LED Interfacing Project
(634)
8.3.6.3.1 Create a Direct Register Access LED Project DRALED
(635)
8.3.6.3.2 Create the C Source File DRALED.c
(635)
8.3.6.3.3 Set Up the Environment to Build and Run the Project
(637)
8.3.7 Build Digital-to-Analog Converter Programming Project
(637)
8.3.7.1 SSI Module Interface for the DAC-MCP4922 in the EduBASE ARM® Trainer
(637)
8.3.7.2 The Operations and Programming for MCP4922 DAC
(638)
8.3.7.3 The Analog-to-Digital Converter TLC-548
(640)
8.3.7.4 Build the Example DAC Interfacing Project
(641)
8.3.7.4.1 Create a Direct Register Access DAC Project DRADAC
(642)
8.3.7.4.2 Create the Header File DRADAC.h
(642)
8.3.7.4.3 Create the C Source File DRADAC.c
(642)
8.3.7.4.4 Set Up the Environment to Build and Run the Project
(645)
8.3.8 SSI API Functions Provided by TivaWare™ Peripheral Driver Library
(646)
8.3.8.1 The SSI Module Initialization and Configuration Functions
(646)
8.3.8.2 The SSI Module Control and Status Functions
(647)
8.3.8.3 The SSI Module Data Processing Functions
(648)
8.3.8.4 The SSI Module Interrupt Source and Processing Functions
(649)
8.3.8.5 Build an Example Project to Interface Serial Peripherals Using the SSI Module
(650)
8.3.8.5.1 Create a New Software Driver Model Project SDLCD
(650)
8.3.8.5.2 Create the Header File SDLCD.h
(650)
8.3.8.5.3 Create the C Source File SDLCD.c
(650)
8.4 Inter-Integrated Circuit (I2c) Interface
(653)
8.4.1 I2C Module Bus Configuration and Operational Status
(654)
8.4.2 I2C Module Architecture and Functional Block Diagram
(655)
8.4.3 I2C Module Data Transfer Format and Frame
(656)
8.4.4 I2C Module Operational Sequence
(656)
8.4.4.1 I2C Module Works in the Master Transmit Mode
(656)
8.4.4.2 I2C Module Works in the Master Receive Mode
(658)
8.4.4.3 I2C Module Works in the Slave Transmit and Receive Modes
(658)
8.4.5 I2C Module Major Operational Components and Control Signals
(660)
8.4.6 I2C Module Running Speeds (Clock Rates) and Interrupts
(662)
8.4.6.1 I2C Module High-Speed Mode
(663)
8.4.6.2 I2C Module Interrupts Generation and Processing
(663)
8.4.6.2.1 I2C Master Interrupts
(664)
8.4.6.2.2 I2C Slave Interrupts
(664)
8.4.7 I2C Interface Control Signals and GPIO I2C Control Registers
(664)
8.4.8 I2C Module Control Registers and Their Functions
(665)
8.4.8.1 I2C Module Master Control Registers
(665)
8.4.8.1.1 I2C Master Slave Address Register (I2CMSA)
(665)
8.4.8.1.2 I2C Master Control/Status Register (I2CMCS)
(666)
8.4.8.1.3 I2C Master Data Register (I2CMDR)
(666)
8.4.8.1.4 I2C Master Timer Period Register (I2CMTPR)
(666)
8.4.8.1.5 I2C Master Configuration Register (I2CMCR)
(667)
8.4.8.1.6 I2C Master Clock Low Timeout Count Register (I2CMCLKOCNT)
(667)
8.4.8.1.7 I2C Master Bus Monitor Register (I2CMBMON)
(668)
8.4.8.1.8 I2C Master Interrupt Mask Register (I2CMIMR)
(668)
8.4.8.1.9 I2C Master Raw Interrupt Status Register (I2CMRIS)
(668)
8.4.8.1.10 I2C Master Masked Interrupt Status Register (I2CMMIS)
(668)
8.4.8.1.11 I2C Master Interrupt Clear Register (I2CMICR)
(669)
8.4.8.2 I2C Module Slave Control Registers
(669)
8.4.8.2.1 I2C Slave Own Address Register (I2CSOAR)
(669)
8.4.8.2.2 I2C Slave Control Status Register (I2CSCSR)
(669)
8.4.8.2.3 I2C Slave Data Register (I2CSDR)
(670)
8.4.8.2.4 I2C Slave Own Address 2 Register (I2CSOAR2)
(670)
8.4.8.2.5 I2C Slave ACK Control Register (I2CSACKCTL)
(670)
8.4.8.2.6 I2C Slave Interrupt Mask Register (I2CSIMR)
(671)
8.4.8.2.7 I2C Slave Raw Interrupt Status Register (I2CSRIS)
(671)
8.4.8.2.8 I2C Slave Masked Interrupt Status Register (I2CSMIS)
(671)
8.4.8.2.9 I2C Slave Interrupt Clear Register (I2CSICR)
(671)
8.4.9 I2C Module Initializations and Configurations
(672)
8.4.9.1 Initializations and Configurations for the I2C-Related GPIO Pins
(672)
8.4.9.2 Initializations and Configurations for the I2C Module
(672)
8.4.10 Build an Example I2C Module Project
(673)
8.4.10.1 The BQ32000 Real Time Clock (RTC)
(673)
8.4.10.2 The Interface Between the BQ32000 and EduBASE ARM® Trainer
(675)
8.4.10.3 Create a DRA Model I2C Project DRAI2C
(676)
8.4.10.4 Create the Source File DRAI2C
(676)
8.4.10.5 Set Up the Environment to Build and Run the Project
(680)
8.4.11 I2C API Functions Provided by TivaWare™ Peripheral Driver Library
(681)
8.4.11.1 Master Operations
(681)
8.4.11.2 I2C Module Status and Initialization API Functions
(682)
8.4.11.3 I2C Module Sending and Receiving Data API Functions
(683)
8.5 Universal Asynchronous Receivers/Transmitters (Uarts)
(684)
8.5.1 Asynchronous Serial Communication Protocols and Data Framing
(684)
8.5.2 Asynchronous Serial Interface Architecture and Functional Block Diagram
(685)
8.5.3 UART Module Operations and Control Registers
(687)
8.5.3.1 Transmit/Receive Logic and Data Transmission and Receiving
(687)
8.5.3.2 UART Modem Handshake Support
(687)
8.5.3.3 UART FIFO Operations
(689)
8.5.3.4 UART Interrupts and DMA Control
(690)
8.5.3.5 UART Serial IR (SIR) Support
(691)
8.5.3.6 9-Bit UART Mode
(691)
8.5.3.7 UART Module Clock Control and Baud Rate Generation Registers
(692)
8.5.3.8 UART Module Control/Status and FIFO Control Registers
(693)
8.5.3.8.1 UART Control Register (UARTCTL)
(693)
8.5.3.8.2 UART Line Control Register (UARTLCRH)
(695)
8.5.3.8.3 UART Receive Status/Error Clear Register (UARTRSR/UARTECR)
(695)
8.5.3.8.4 UART Data Register (UARTDR)
(696)
8.5.3.8.5 UART Flag Register (UARTFR)
(697)
8.5.3.9 UART Module Interrupt and DMA Control Registers
(697)
8.5.3.9.1 UART Interrupt FIFO Level Select (UARTIFLS) Register
(698)
8.5.3.9.2 UART Raw Interrupt Status (UARTRIS) Register
(698)
8.5.3.9.3 UART Interrupt Mask (UARTIM) Register
(698)
8.5.3.9.4 UART Masked Interrupt Status (UARTMIS) Register
(699)
8.5.3.9.5 UART Interrupt Clear Register (UARTICR)
(699)
8.5.3.9.6 UART DMA Control (UARTDMACTL) Register
(699)
8.5.4 UART Module Control Signals and Related GPIO Pins
(700)
8.5.5 UART Module Initializations and Configurations
(701)
8.5.5.1 Initialize and Configure the UART-Related GPIO Ports and Pins
(701)
8.5.5.2 Initialize and Configure Clock Source and Baud Rate for the UART Module
(701)
8.5.5.3 Initialize and Configure the UART Module
(702)
8.5.6 Build an Example UART Module Project
(702)
8.5.6.1 Create a New UART Module Project DRAUART
(703)
8.5.6.2 Create a New C Source File
(703)
8.5.6.3 Set Up the Environment to Build and Run the Project
(706)
8.5.7 The UART API Functions Provided by the TivaWare™ Peripheral Driver Library
(706)
8.5.7.1 Clock Source for the Baud Rate Generator API Functions
(707)
8.5.7.2 Configure and Control the UART Modules API Functions
(708)
8.5.7.3 UART Send and Receive Data API Functions
(709)
8.5.7.4 UART Interrupt Handling API Functions
(709)
8.6 Chapter Summary
(710)
Homework
(711)
9: ARM® Cortex®-M4 Timer and USB Programming
(733)
9.1 Overview and Introduction
(733)
9.2 General-Purpose Timers
(734)
9.2.1 The GPTM Architecture and Functional Block Diagram
(735)
9.2.2 The General-Purpose Timer Module Components
(736)
9.2.2.1 Prescaler Registers
(737)
9.2.2.2 Match Registers
(737)
9.2.2.3 Shadow Registers
(737)
9.2.3 The General-Purpose Timer Module Operational Modes
(737)
9.2.3.1 One-Shot and Periodic Timer Mode
(738)
9.2.3.2 Periodic Snapshot Timer Mode
(740)
9.2.3.3 Wait-for-Trigger Mode
(741)
9.2.3.4 Real-Time Clock Timer Mode
(741)
9.2.3.5 Input Edge-Count Mode
(741)
9.2.3.6 Input Edge-Time Mode
(742)
9.2.3.7 PWM Mode
(744)
9.2.3.8 DMA Mode
(745)
9.2.3.9 Synchronizing GP Timer Blocks
(745)
9.2.3.10 Concatenated Modes
(745)
9.2.4 The General-Purpose Timer Module Registers
(746)
9.2.4.1 Timer A Control Register Group
(746)
9.2.4.1.1 GPTM Configuration Register (GPTMCFG)
(747)
9.2.4.1.2 GPTM Control Register (GPTMCTL)
(747)
9.2.4.1.3 GPTM Timer A Mode Register (GPTMTAMR)
(747)
9.2.4.1.4 GPTM Timer A Interval Load Register (GPTMTAILR)
(747)
9.2.4.1.5 GPTM Timer A Match Register (GPTMTAMATCHR)
(748)
9.2.4.1.6 GPTM Timer A Prescale Register (GPTMTAPR)
(749)
9.2.4.1.7 GPTM Timer A Prescale Match Register (GPTMTAPMR)
(750)
9.2.4.1.8 GPTM Timer A Prescale Snapshot Register (GPTMTAPS)
(750)
9.2.4.2 Timer A Status Register Group
(750)
9.2.4.2.1 GPTM Timer A Register (GPTMTAR)
(750)
9.2.4.2.2 GPTM Timer A Value Register (GPTMTAV)
(751)
9.2.4.2.3 GPTM Timer A Prescale Value Register (GPTMTAPV)
(751)
9.2.4.3 Timers A and B Interrupt and Configuration Register Group
(751)
9.2.4.3.1 GPTM Interrupt Mask Register (GPTMIMR)
(752)
9.2.4.3.2 GPTM Raw Interrupt Status Register (GPTMRIS)
(753)
9.2.4.3.3 GPTM Masked Interrupt Status Register (GPTMMIS)
(753)
9.2.4.3.4 GPTM Interrupt Clear Register (GPTMICR)
(753)
9.2.4.3.5 GPTM Synchronize Register (GPTMSYNC)
(753)
9.2.4.3.6 GPTM Peripheral Properties Register (GPTMPP)
(753)
9.2.5 The General-Purpose Timer Module GPIO-Related Control Signals
(754)
9.2.6 The General-Purpose Timer Module Initializations and Configurations
(755)
9.2.6.1 Initialization and Configuration for One-Shot/Periodic Timer Mode
(756)
9.2.6.2 Initialization and Configuration for Input Edge-Count Mode
(756)
9.2.6.3 Initialization and Configuration for Input Edge-Time Mode
(757)
9.2.6.4 Initialization and Configuration for Real-Time Clock (RTC) Mode
(758)
9.2.6.5 Initialization and Configuration for PWM Mode
(758)
9.2.7 Build an Example General Purpose Timer Project
(759)
9.2.8 Popular Implementations on GPTM Modules
(760)
9.2.8.1 Input Edge-Count Implementations
(761)
9.2.8.2 Input Edge-Time Implementations
(763)
9.2.8.3 PWM Implementations
(765)
9.2.9 The API Functions Used for General-Purpose Timer Module
(769)
9.2.9.1 The API Functions Used for GPTM Module Configurations and Controls
(769)
9.2.9.2 The API Functions Used for GPTM Module Contents and Related Operations
(769)
9.2.9.3 The API Functions Used for GPTM Module Interrupt Handling
(772)
9.2.9.4 An Implementation of Using Timer API Functions to Measure PWM Pulses
(773)
9.3 Watchdog Timers
(774)
9.3.1 The Watchdog Timer Architecture and Functional Block Diagram
(776)
9.3.2 The Watchdog Timer Operational Sequence and Timing Access
(777)
9.3.3 The Watchdog Timer Registers
(777)
9.3.3.1 The Watchdog Module Control and Content Registers
(777)
9.3.3.1.1 Watchdog Timer Control Register (WDTCTL)
(778)
9.3.3.1.2 Watchdog Timer Load Register (WDTLOAD)
(778)
9.3.3.1.3 Watchdog Timer Value Register (WDTVALUE)
(778)
9.3.3.1.4 Watchdog Timer Lock Register (WDTLOCK)
(778)
9.3.3.1.5 Watchdog Timer Test Register (WDTTEST)
(779)
9.3.3.2 The Watchdog Module Interrupt Handling Registers
(779)
9.3.3.2.1 Watchdog Raw Interrupt Status Register (WDTRIS)
(779)
9.3.3.2.2 Watchdog Masked Interrupt Status Register (WDTMIS)
(779)
9.3.3.2.3 Watchdog Interrupt Clear Register (WDTICR)
(779)
9.3.3.2.4 Watchdog Timer Software Reset Register (SRWD)
(780)
9.3.4 The Watchdog Timer Module Initializations and Configurations
(780)
9.3.5 Build an Example Watchdog Timer Project
(781)
9.3.6 The API Functions Used for Watchdog Timer Modules
(781)
9.3.6.1 The API Functions Used to Configure and Control the Watchdog Timers
(782)
9.3.6.2 The API Functions Used to Handle Interrupts of the Watchdog Timers
(784)
9.3.6.3 An Implementation Example of Using API Functions to Control the Watchdog Timer
(785)
9.4 Universal Serial Bus (Usb) Controller
(785)
9.4.1 The Hardware Configuration of the USB Devices
(786)
9.4.2 The USB Components and Operational Sequence
(787)
9.4.3 The Serial Interface Protocol of the USB Communications
(789)
9.4.4 The USB Interface Used in the Embedded System
(790)
9.4.5 The USB in the TM4C123GH6PM MCU System
(791)
9.4.5.1 USB Working as a Device
(791)
9.4.5.1.1 IN Transactions as a Device
(792)
9.4.5.1.2 OUT Transactions as a Device
(793)
9.4.5.1.3 Other Device Functions
(794)
9.4.5.2 USB Working as a Host
(796)
9.4.5.2.1 IN Transactions as a Host
(797)
9.4.5.2.2 OUT Transactions as a Host
(797)
9.4.5.2.3 Transactions Scheduling
(798)
9.4.5.2.4 Other Host Functions
(798)
9.4.5.3 The OTG Mode
(799)
9.4.5.3.1 Using OTG to Start a Session
(800)
9.4.5.3.2 Using OTG to Perform Detecting Activity
(801)
9.4.5.3.3 Using OTG to Perform Host Negotiation
(801)
9.4.5.4 The USB Module Functional Block Diagram
(801)
9.4.5.5 The USB Module Control Signals
(802)
9.4.6 The USB Registers
(803)
9.4.6.1 USB Host-Related Registers
(804)
9.4.6.2 USB Device-Related Registers
(805)
9.4.6.3 USB Host/Device-Related Registers
(806)
9.4.6.4 USB FIFO-Related Registers
(807)
9.4.6.5 USB-Interrupt-Related Registers
(813)
9.4.7 The USB Initializations and Configurations
(816)
9.4.7.1 Enable and Clock the USB Controller and Related GPIO Ports and Pins
(816)
9.4.7.2 USB Control Pins Configurations
(816)
9.4.7.3 Endpoint Configurations
(817)
9.4.8 A USB Implementation Example Project
(817)
9.4.9 The USB API Functions Provided by the TivaWare™ Peripheral Driver Library
(822)
9.4.9.1 The USBClock and USBMode API Functions
(823)
9.4.9.2 The USBDev API Functions
(823)
9.4.9.3 The USBHost API Functions
(825)
9.4.9.4 The USBEndpoint API Functions
(826)
9.4.9.5 The USBFIFO API Functions
(828)
9.4.9.6 The USBInterrupt API Functions
(828)
9.4.9.7 The USBOTG API Functions
(830)
9.4.10 Build a USB Implementation Example Project Using the API Functions
(830)
9.5 Chapter Summary
(830)
Homework
(832)
10: ARM® Cortex®-M4 Other Peripherals Programming
(847)
10.1 Overview and Introduction
(847)
10.2 The Controller Area Network (Can)
(847)
10.2.1 CAN Standard Frame
(848)
10.2.2 CAN Extended Frame
(849)
10.2.3 Detecting and Signaling Errors
(850)
10.2.4 The CAN Functional Block Diagram in the TM4C123GH6PM System
(851)
10.2.5 The CAN Components and Operational Procedures
(852)
10.2.5.1 CAN Initialization and Configuration Process
(853)
10.2.5.2 Transmit Message Objects
(854)
10.2.5.3 Receive Message Objects
(857)
10.2.5.4 Handle CAN Module Interrupts
(859)
10.2.5.5 CAN Module Operational Modes
(860)
10.2.5.6 CAN Clock and Baud Rate Configuration
(861)
10.2.5.6.1 Calculate the Bit Time Parameters and Configure the CANBIT Register
(863)
10.2.6 The CAN Module Registers
(865)
10.2.6.1 The CAN Global Control and Status Registers
(865)
10.2.6.1.1 The CAN Global Control Register (CANCTL)
(865)
10.2.6.1.2 The CAN Global Status Register (CANSTS)
(866)
10.2.6.1.3 The CAN Error Counter Register (CANERR)
(867)
10.2.6.1.4 The CAN Bit Timing Register (CANBIT)
(867)
10.2.6.1.5 The CAN Test Register (CANTST)
(868)
10.2.6.1.6 The CAN Baud Rate Prescaler Extension Register (CANBRPE)
(868)
10.2.6.1.7 The CAN Interrupt Register (CANINT)
(869)
10.2.6.2 The CAN Interface 1 Registers
(870)
10.2.6.2.1 CAN IF1 Command Request Register (CANIF1CRQ)
(870)
10.2.6.2.2 CAN IF1 Command Mask Register (CANIF1CMSK)
(870)
10.2.6.2.3 CAN IF1 Message Control Register (CANIF1MCTL)
(872)
10.2.6.2.4 CAN IF1 Mask 1 Register (CANIF1MSK1)
(873)
10.2.6.2.5 CAN IF1 Mask 2 Register (CANIF1MSK2)
(873)
10.2.6.2.6 CAN IF1 Arbitration 1 Register (CANIF1ARB1)
(873)
10.2.6.2.7 CAN IF1 Arbitration 2 Register (CANIF1ARB2)
(874)
10.2.6.2.8 CAN IF1 Data A1, CAN IF1 Data A2, CAN IF1 Data B1, CAN IF1 Data B2 (CANIF1DA1~CANIF1DA2, CANIF1DB1~CANIF1DB2) Registers
(874)
10.2.6.3 The CAN Message Object Registers
(875)
10.2.7 The CAN Module Interfacing and External Control Signals
(875)
10.2.8 The CAN API Functions Provided by TivaWare™ Peripheral Driver Library
(876)
10.2.8.1 Special Data Structures and Enumerations Used in the CAN Programming
(876)
10.2.8.2 CAN Module Initialization and Configuration Functions
(877)
10.2.8.3 CAN Module Message Setting and Processing Functions
(878)
10.2.8.4 CAN Module Interrupt Configuration and Handle Functions
(880)
10.2.9 A CAN Module Implementation Example Project
(880)
10.2.9.1 Build a Simple CAN Self-Test Project
(881)
10.2.9.2 Build the Header File for the CAN Project CANLoopBack
(882)
10.2.9.3 Build the Source File for the CAN Project CANLoopBack
(883)
10.2.9.4 Set Up the Environment to Build and Run the Project
(888)
10.3 The Quadrature Encoder Interface (Qei)
(889)
10.3.1 Introduction to Quadrature Encoder
(889)
10.3.2 The Working Principle of the Increment Rotary Encoder
(891)
10.3.3 The Increment Rotary Encoder Applied in the Closed-Loop Control System
(892)
10.3.4 The Increment Rotary Encoder Applied in the TM4C123GH6PM MCU System
(893)
10.3.5 The QEI Module Registers
(894)
10.3.5.1 QEI Control and Status Registers
(894)
10.3.5.2 QEI Position Control Registers
(896)
10.3.5.3 QEI Velocity Control Registers
(897)
10.3.5.4 QEI Interrupt Processing Registers
(897)
10.3.6 The QEI Interfacing Signals and Related GPIO Pins
(898)
10.3.7 The QEI Initialization and Configuration Process
(898)
10.3.8 QEI API Functions Provided by the TivaWare™ Peripheral Driver Library
(899)
10.3.8.1 QEI Configuration and Enable API Functions
(900)
10.3.8.2 QEI Position Capture API Functions
(900)
10.3.8.3 QEI Velocity Capture API Functions
(901)
10.3.8.4 QEI Interrupt Handling API Functions
(901)
10.3.9 An Implementation of Using Rotary Encoder for a Closed-Loop Control System
(902)
10.3.9.1 Calibration of the Rotary Encoder
(903)
10.3.9.2 Build the Floating Chart for the Motor Closed-Loop Control System
(909)
10.3.9.3 Build the Closed-Loop Control Program Based on the Floating Chart
(911)
10.4 The Continuous and Discrete Pid Closed-Loop Control System
(913)
10.4.1 Identify the Dynamic Model for the Motor Plant
(915)
10.4.1.1 Format the Input and Output Data for the DC Motor
(916)
10.4.1.2 Identify the DC Motor Dynamic Model with Identification Toolbox™
(918)
10.4.2 Design the PID Controller Using the MATLAB® Control System Toolbox™
(920)
10.4.3 Simulate the PID Control System Using the MATLAB® SIMULINK®
(923)
10.4.4 Build the Control Software to Implement the PID Controller
(925)
10.5 The Fuzzy Logic Closed-Loop Control System
(929)
10.5.1 The Fuzzification Process
(929)
10.5.2 Design of Control Rules
(931)
10.5.3 The Defuzzification Process
(931)
10.5.4 Apply the Fuzzy Logic Controller to the DC Motor Control System
(933)
10.5.5 Build the Fuzzy Logic Control Project Fuzzy-Control
(936)
10.5.5.1 Create the Header File Fuzzy-Control.h
(936)
10.5.5.2 Create the C Source File Fuzzy-Control.c
(937)
10.5.5.3 Set Up Environments to Build and Run the Project
(940)
10.6 The Analog Comparators
(941)
10.6.1 The Analog Comparator Architecture and Functional Block Diagram
(941)
10.6.2 The Control Registers Used in the Analog Comparator Modules
(941)
10.6.3 The Voltage Reference Registers Used in the Analog Comparator Modules
(942)
10.6.4 The Interrupt Processing Registers Used in the Analog Comparator Modules
(945)
10.6.5 The Input and Output Control Signals Used in the Analog Comparators
(945)
10.6.6 The Initialization and Configuration Process for the Analog Comparator
(946)
10.6.7 Build a Project to Test the Functions of the Analog Comparator Module
(946)
10.6.8 Set Up the Environments to Build and Run the Project
(949)
10.7 Chapter Summary
(950)
Homework
(951)
11: ARM® Floating Point Unit (FPU)
(969)
11.1 Overview and Introduction
(969)
11.2 Three Types of the Floating-Point Data
(970)
11.2.1 The Half-Precision Floating-Point Data
(970)
11.2.2 The Single-Precision Floating-Point Data
(972)
11.2.3 The Double-Precision Floating-Point Data
(974)
11.3 The FPU in the Cortex®-M4 MCU
(976)
11.3.1 The Architecture of the Floating-Point Registers
(976)
11.3.2 The FPU Operational Modes
(979)
11.4 Implementing the Floating-Point Unit
(980)
11.4.1 Floating-Point Support in CMSIS-Core
(980)
11.4.2 Floating-Point Programming in the TM4C123GH6PM MCU System
(981)
11.4.2.1 FPU in the Direct Register Access Model
(982)
11.4.2.2 FPU in the Software Driver Model
(984)
11.4.3 A FPU Example Project Using the Direct Register Access Model
(984)
11.5 Chapter Summary
(988)
Homework
(988)
12: ARM® Memory Protection Unit (MPU)
(993)
12.1 Overview and Introduction
(993)
12.2 Implementation of the Mpu
(994)
12.2.1 Memory Regions, Types, and Attributes
(995)
12.2.2 MPU Configuration and Control Registers
(995)
12.2.2.1 The MPU Type Register (MPUTYPE)
(996)
12.2.2.2 The MPU Control Register (MPUCTRL)
(996)
12.2.2.3 The MPU Region Number Register (MPUNUMBER)
(998)
12.2.2.4 MPU Region Base Address Register (MPUBASE)
(998)
12.2.2.5 The MPU Region Attribute and Size Register (MPUATTR)
(999)
12.3 Initialization and Configuration of the Mpu
(1001)
12.4 Building a Practical Example Mpu Project
(1002)
12.4.1 Create a New DRA Model MPU Project DRAMPU
(1002)
12.4.2 Set Up the Environment to Build and Run the Project
(1005)
12.5 The Api Functions Provided By the Tivaware™ Peripheral Driver Library
(1006)
12.5.1 The MPU Set Up and Status API Functions
(1007)
12.5.1.1 The API Function MPURegionSet()
(1008)
12.5.2 The MPU Enable and Disable API Functions
(1009)
12.5.3 The MPU Interrupt Handler Control API Functions
(1010)
12.6 Chapter Summary
(1011)
Homework
(1012)
Index
(1017)
About the Author
(1029)
End User License Agreement
(1031)
