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Practical microcontroller engineering with ARM® technology
Bai, Ying,
- ISBN:1119052378
- ISBN:9781119052371
- Call Number : TJ 223 .P76 .B25 2016
- Main Entry: Bai, Ying, 1956- author.
- Title:Practical microcontroller engineering with ARM® technology / Ying Bai.
- Publisher:Hoboken, New Jersey : Wiley, 2016.
- Physical Description:xxxix, 987 p.: ill. ; 24 cm
- Notes: "Also in electronic format is available"
- Notes:Includes index
- Subject:Microcontrollers.
- Subject:Programmable controllers.
Practical microcontroller engineering withمحتواي کتاب
- Practical Microcontroller Engineering with ARM® Technology
- Contents
- Preface
- Acknowledgments
- Trademarks and Copyrights
- Copyright Permissions
- About the Companion Website
- 1: Introduction to Microcontrollers and This Book
- 1.1 Microcontroller Configuration and Structure
- 1.2 The Arm® Cortex®M4 Microcontroller System
- 1.3 The Tm4c123gh6pm Microcontroller Development Tools and Kits
- 1.4 Outstanding Features About This Book
- 1.5 Who This Book Is For
- 1.6 What This Book Covers
- 1.7 How This Book Is Organized and How to Use This Book
- 1.8 How to Use the Source Code and Sample Projects
- 1.9 Instructors and Customers Supports
- 2: ARM® Microcontroller Architectures
- 2.1 Overview and Introduction
- 2.2 Introduction to Arm® Cortex®-M4 Mcu
- 2.3 The Memory Architecture
- 2.4 The Nested Vectored Interrupt Controller (Nvic) Architecture
- 2.5 The Debug Architecture
- 2.6 Introduction to Tiva™ C Series Arm® Cortex®-M4 Mcu - Tm4c123gh6pm
- 2.6.1 TM4C123GH6PM Microcontroller Overview
- 2.6.2 TM4C123GH6PM Microcontroller On-Chip Memory Map
- 2.6.3 TM4C123GH6PM Microcontroller General-Purpose Input-Output (GPIO) Module
- 2.6.4 TM4C123GH6PM Microcontroller System Controls
- 2.7 Introduction to Tiva™ C Series Launchpad™ Tm4c123gxl Evaluation Board
- 2.8 Introduction to Edubase Arm® Trainer
- 2.9 Chapter Summary
- Homework
- 3: ARM® Microcontroller Development Kits
- 3.1 Overview and Introduction
- 3.2 The Entire Tiva™ Tm4c123g-Based Development System
- 3.3 Download and Install Development Suite and Specified Firmware
- 3.4 Introduction to the Integrated Development Environment-Keil® Mdk Μversion5
- 3.5 Embedded Software Development Procedure
- 3.6 The Keil® Arm®-Mdk μvision5 Debugger and Debug Process
- 3.6.1 The ARM® μVision5 Debug Architecture
- 3.6.2 The ARM® Debug Adaptor and Debug Adaptor Driver
- 3.6.3 Tiva™ C Series LaunchPad™ Debug Adaptor and Debug Adaptor Driver
- 3.6.4 The ARM® μVersion5 Debug Process
- 3.6.5 The ARM® Trace Feature
- 3.6.6 The ARM® Instruction Set Simulator
- 3.6.7 The ARM® Programs Running from SRAM
- 3.6.8 ARM® Optimizations
- 3.7 The Tivaware™ for C Series Software Suite
- 3.8 The Tivaware™ for C Series Utilities and Other Supports
- 3.9 Program Examples
- 3.10 Chapter Summary
- Homework
- 4: ARM® Microcontroller Software and Instruction Set
- 4.1 Overview and Introduction
- 4.2 Introduction to Arm® Cortex®-M4 Software Development Structure
- 4.3 Introduction to Arm® Cortex®-M4 Assembly Instruction Set
- 4.3.1 The ARM® Cortex®-M4 Assembly Language Syntax
- 4.3.2 The ARM® Cortex®-M4 Pseudo Instructions
- 4.3.3 The ARM® Cortex®-M4 Addressing Modes
- 4.3.3.1 The Immediate Offset Addressing Mode
- 4.3.3.2 The Register Offset Addressing Mode
- 4.3.3.3 The PC-Relative Addressing Mode
- 4.3.3.4 Load and Store Multiple Registers Addressing Mode
- 4.3.3.5 PUSH and POP Register Addressing Mode
- 4.3.3.6 Load and Store Register Exclusive Addressing Mode
- 4.3.3.7 Inherent Addressing Mode
- 4.3.3.8 Addressing Mode Summary
- 4.3.4 The ARM® Cortex®-M4 Instruction Set Categories
- 4.3.4.1 Data Moving Instructions
- 4.3.4.2 Arithmetic Instructions
- 4.3.4.3 Logic Instructions
- 4.3.4.4 Shift and Rotate Instructions
- 4.3.4.5 Data Conversion Instructions
- 4.3.4.6 Bit-Field Processing Instructions
- 4.3.4.7 Compare and Test Instructions
- 4.3.4.8 Program Flow Control Instructions
- 4.3.4.9 Saturation Instructions
- 4.3.4.10 Exception-Related Instructions
- 4.3.4.11 Sleep Mode Instructions
- 4.3.4.12 Memory Barrier Instructions
- 4.3.4.13 Miscellaneous Instructions
- 4.3.4.14 Unsupported Instructions
- 4.4 Arm® Cortex®-M4 Software Development Procedures
- 4.5 Using C Language to Develop Arm® Cortex®-M4 Microcontroller Applications
- 4.5.1 The Standard Data Types Used in Intrinsic Functions
- 4.5.2 The CMSIS-Core-Specific Intrinsic Functions
- 4.5.3 The Keil® ARM® Compiler-Specific Intrinsic Functions
- 4.5.4 Inline Assembler
- 4.5.5 Idiom Recognition
- 4.5.6 C Programming Development Guideline and Procedure
- 4.5.7 The TivaWare™ Peripheral Driver Library
- 4.6 Chapter Summary
- Homework
- 5: ARM® Microcontroller Interrupts and Exceptions
- 5.1 Overview and Introduction
- 5.2 Exceptions and Interrupts in the Arm® Cortex®-M4 Mcu System
- 5.3 Exceptions and Interrupts in the Tm4c123gh6pm Microcontroller System
- 5.4 Developing Gpio Port Interrupt Projects to Handle Gpio Interrupts
- 5.4.1 Two Software Packages Used in the TM4C123GH6PM MCU System
- 5.4.2 Using DRA Programming Model to Handle GPIO Interrupts
- 5.4.3 Using CMSIS Core Macros for NVIC Registers to Handle GPIO Interrupts
- 5.4.3.1 Popular Data Structures Defined in the CMSIS Core Header File
- 5.4.3.2 IRQ Numbers Defined in the TivaWare™ System Header File
- 5.4.3.3 The NVIC Macros Defined in the TivaWare™ System Header Files
- 5.4.3.4 The NVIC Structure Defined in the CMSIS Core Header File
- 5.4.3.5 Building Sample Project to Use CMSIS Core Macros for NVIC to Handle Interrupts
- 5.4.3.6 Create a New Project NVICInt and Add the C Code File
- 5.4.4 Using TivaWare™ Peripheral Driver Library API Functions to Handle GPIO Interrupts
- 5.4.4.1 NVIC API Functions Defined in the TivaWare™ Peripheral Driver Library
- 5.4.4.2 GPIO Interrupt-Related API Functions in the TivaWare™ Peripheral Driver Library
- 5.4.4.3 Building Sample Project to Use Peripheral Driver Library to Handle Interrupts
- 5.4.4.4 Create a New Project SDInt and Add the C Code File
- 5.4.4.5 Configuring the Environments and Run the Project
- 5.4.5 Using CMSIS Core Access Functions to Handle GPIO Interrupts
- 5.5 Comparison Among Four Interrupt Programming Methods
- 5.6 Chapter Summary
- Homework
- 6: ARM® Microcontroller Memory System
- 6.1 Overview and Introduction
- 6.2 Memory Architecture in the Tm4c123gh6pm Mcu System
- 6.2.1 Static Random Access Memory (SRAM)
- 6.2.2 Flash Memory
- 6.2.2.1 Basic Operations of the Flash Memory
- 6.2.2.2 The 32-Word Flash Memory Write Buffer
- 6.2.2.3 Flash Control Registers
- 6.2.2.4 Boot Configuration Register (BOOTCFG)
- 6.2.2.5 Flash Memory Address Register (FMA)
- 6.2.2.6 Flash Memory Data Register (FMD)
- 6.2.2.7 Flash Memory Control Register (FMC)
- 6.2.2.8 Flash Memory Control 2 Register (FMC2)
- 6.2.2.9 The Flash Write Buffer Valid Register (FWBVAL)
- 6.2.2.10 Flash Controller Raw Interrupt Status Register (FCRIS)
- 6.2.2.11 Flash Controller Interrupt Mask Register (FCIM)
- 6.2.2.12 Flash Controller Masked Interrupt Status and Clear Register (FCMISC)
- 6.2.2.13 Other Control Registers Related to Flash Memory Control
- 6.2.3 Flash Memory Protection Control
- 6.2.4 Internal Read-Only Memory (ROM)
- 6.2.5 Electrical Erased Programmable Read-Only Memory (EEPROM)
- 6.3 Memory Map in Tm4c123gh6pm Mcu System
- 6.4 Bit-Band Operations
- 6.5 Memory Requirements and Memory Properties
- 6.6 Memory System Programming Methods
- 6.7 Memory System Programming Projects
- 6.7.1 Flash Memory Programming
- 6.7.2 EEPROM Programming
- 6.7.3 Three Kinds of System Header Files in TM4C123GH6PM MCU System
- 6.7.4 Build Example EEPROM Programming Projects
- 6.8 Chapter Summary
- Homework
- 7: ARM® Cortex®-M4 Parallel I/O Ports Programming
- 7.1 Overview and Introduction
- 7.2 Gpio Module Architecture and Gpio Port Configuration
- 7.3 Gpio Port Control Registers
- 7.4 On-Board Keypad Interface Programming Project
- 7.5 Analog-To-Digital Converter Programming Project
- 7.5.1 ADC Modules in the TM4C123GH6PM MCU System
- 7.5.2 ADC Module Architecture and Functional Block Diagram
- 7.5.3 ADC Module Components and Signal Descriptions
- 7.5.3.1 Analog Input Signals and GPIO Analog Control Registers
- 7.5.3.2 Sample Sequencer Controls and Their Control Registers
- 7.5.3.2.1 ADC Sample Sequencer Input Multiplexer Select (ADCSSMUXn) Register
- 7.5.3.2.2 ADC Sample Sequencer Control (ADCSSCTLn) Register
- 7.5.3.2.3 ADC Active Sample Sequencer (ADCACTSS) Register
- 7.5.3.2.4 ADC Processor Sample Sequencer Initiate (ADCPSSI) Register
- 7.5.3.2.5 ADC Sample Sequencer Result FIFO (ADCSSFIFOn) Register
- 7.5.3.3 ADC Module Control Functions and Related Registers
- 7.5.4 Analog-to-Digital Converter
- 7.5.5 Initialization and Configuration
- 7.5.6 Build the Analog-to-Digital Converter Programming Project
- 7.5.7 ADC Module API Functions Provided in the TivaWare™ Peripheral Driver Library
- 7.6 Pwm-Controlled Dc and Step Motors Programming Project
- 7.6.1 The PWM Principle and Implementations
- 7.6.2 PWM Modules in the TM4C123GH6PM MCU System
- 7.6.3 PWM Generator Functional Block Diagram
- 7.6.3.1 PWM Generator Block Control Register (PWMnCTL)
- 7.6.3.2 PWM Generator Block Load Register (PWMnLOAD)
- 7.6.3.3 PWM Generator Block Count Register (PWMnCOUNT)
- 7.6.3.4 PWM Generator Block Comparator A Register (PWMnCMPA)
- 7.6.3.5 PWM Generator Block Comparator B Register (PWMnCMPB)
- 7.6.3.6 PWM Generator A Register (PWMnGENA)
- 7.6.3.7 PWM Generator B Register (PWMnGENB)
- 7.6.3.8 PWM Generator Dead-Band Control Register (PWMnDBCTL)
- 7.6.3.9 PWM Generator Dead-Band Rising-Edge Delay Register (PWMnDBRISE)
- 7.6.3.10 PWM Generator Dead-Band Falling-Edge Delay Register (PWMnDBFALL)
- 7.6.3.11 PWM Interrupt and Trigger Enable Register (PWMnINTEN)
- 7.6.3.12 PWM Raw Interrupt Status Register (PWMnRIS)
- 7.6.3.13 PWM Interrupt Status and Clear Register (PWMnISC)
- 7.6.3.14 PWM Fault Source n Register (PWMFLTSRCn)
- 7.6.4 PWM Module Architecture and Functional Block Diagram
- 7.6.5 PWM Module Components and Signal Descriptions
- 7.6.6 PWM Module Initialization and Configuration
- 7.6.7 PWM Module Architecture in the EduBASE ARM® Trainer
- 7.6.8 Build an Example PWM Programming Project
- 7.7 The Pwm Api Functions in the Tivaware™ Peripheral Driver Library
- 7.8 Chapter Summary
- Homework
- 8: ARM® Cortex®-M4 Serial I/O Ports Programming
- 8.1 Overview and Introduction
- 8.2 Gpio Module Architecture and Gpio Port Configuration
- 8.3 Synchronous Serial Interface (Ssi)
- 8.3.1 Asynchronous and Synchronous Communication Protocols and Data Framing
- 8.3.2 Synchronous Serial Interface Architecture and Functional Block Diagram
- 8.3.3 The Synchronous Data Transmission Format and Frame
- 8.3.4 SSI Module Components and Signal Descriptions
- 8.3.4.1 SSI Control Signals and GPIO SSI Control Registers
- 8.3.4.2 SSI Module Bit Rate Generation and Clock Control
- 8.3.4.3 SSI Module Control/Status and FIFO Control
- 8.3.4.4 SSI Module Interrupt and DMA Control
- 8.3.4.5 SSI Module Transmit/Receive Logic Control
- 8.3.4.6 SSI Modules Initialization and Configurations
- 8.3.5 Build the On-Board LCD Interface Programming Project
- 8.3.6 Build On-Board 7-Segment LED Interface Programming Project
- 8.3.7 Build Digital-to-Analog Converter Programming Project
- 8.3.8 SSI API Functions Provided by TivaWare™ Peripheral Driver Library
- 8.3.8.1 The SSI Module Initialization and Configuration Functions
- 8.3.8.2 The SSI Module Control and Status Functions
- 8.3.8.3 The SSI Module Data Processing Functions
- 8.3.8.4 The SSI Module Interrupt Source and Processing Functions
- 8.3.8.5 Build an Example Project to Interface Serial Peripherals Using the SSI Module
- 8.4 Inter-Integrated Circuit (I2c) Interface
- 8.4.1 I2C Module Bus Configuration and Operational Status
- 8.4.2 I2C Module Architecture and Functional Block Diagram
- 8.4.3 I2C Module Data Transfer Format and Frame
- 8.4.4 I2C Module Operational Sequence
- 8.4.5 I2C Module Major Operational Components and Control Signals
- 8.4.6 I2C Module Running Speeds (Clock Rates) and Interrupts
- 8.4.7 I2C Interface Control Signals and GPIO I2C Control Registers
- 8.4.8 I2C Module Control Registers and Their Functions
- 8.4.8.1 I2C Module Master Control Registers
- 8.4.8.1.1 I2C Master Slave Address Register (I2CMSA)
- 8.4.8.1.2 I2C Master Control/Status Register (I2CMCS)
- 8.4.8.1.3 I2C Master Data Register (I2CMDR)
- 8.4.8.1.4 I2C Master Timer Period Register (I2CMTPR)
- 8.4.8.1.5 I2C Master Configuration Register (I2CMCR)
- 8.4.8.1.6 I2C Master Clock Low Timeout Count Register (I2CMCLKOCNT)
- 8.4.8.1.7 I2C Master Bus Monitor Register (I2CMBMON)
- 8.4.8.1.8 I2C Master Interrupt Mask Register (I2CMIMR)
- 8.4.8.1.9 I2C Master Raw Interrupt Status Register (I2CMRIS)
- 8.4.8.1.10 I2C Master Masked Interrupt Status Register (I2CMMIS)
- 8.4.8.1.11 I2C Master Interrupt Clear Register (I2CMICR)
- 8.4.8.2 I2C Module Slave Control Registers
- 8.4.8.2.1 I2C Slave Own Address Register (I2CSOAR)
- 8.4.8.2.2 I2C Slave Control Status Register (I2CSCSR)
- 8.4.8.2.3 I2C Slave Data Register (I2CSDR)
- 8.4.8.2.4 I2C Slave Own Address 2 Register (I2CSOAR2)
- 8.4.8.2.5 I2C Slave ACK Control Register (I2CSACKCTL)
- 8.4.8.2.6 I2C Slave Interrupt Mask Register (I2CSIMR)
- 8.4.8.2.7 I2C Slave Raw Interrupt Status Register (I2CSRIS)
- 8.4.8.2.8 I2C Slave Masked Interrupt Status Register (I2CSMIS)
- 8.4.8.2.9 I2C Slave Interrupt Clear Register (I2CSICR)
- 8.4.8.1 I2C Module Master Control Registers
- 8.4.9 I2C Module Initializations and Configurations
- 8.4.10 Build an Example I2C Module Project
- 8.4.11 I2C API Functions Provided by TivaWare™ Peripheral Driver Library
- 8.5 Universal Asynchronous Receivers/Transmitters (Uarts)
- 8.5.1 Asynchronous Serial Communication Protocols and Data Framing
- 8.5.2 Asynchronous Serial Interface Architecture and Functional Block Diagram
- 8.5.3 UART Module Operations and Control Registers
- 8.5.3.1 Transmit/Receive Logic and Data Transmission and Receiving
- 8.5.3.2 UART Modem Handshake Support
- 8.5.3.3 UART FIFO Operations
- 8.5.3.4 UART Interrupts and DMA Control
- 8.5.3.5 UART Serial IR (SIR) Support
- 8.5.3.6 9-Bit UART Mode
- 8.5.3.7 UART Module Clock Control and Baud Rate Generation Registers
- 8.5.3.8 UART Module Control/Status and FIFO Control Registers
- 8.5.3.9 UART Module Interrupt and DMA Control Registers
- 8.5.3.9.1 UART Interrupt FIFO Level Select (UARTIFLS) Register
- 8.5.3.9.2 UART Raw Interrupt Status (UARTRIS) Register
- 8.5.3.9.3 UART Interrupt Mask (UARTIM) Register
- 8.5.3.9.4 UART Masked Interrupt Status (UARTMIS) Register
- 8.5.3.9.5 UART Interrupt Clear Register (UARTICR)
- 8.5.3.9.6 UART DMA Control (UARTDMACTL) Register
- 8.5.4 UART Module Control Signals and Related GPIO Pins
- 8.5.5 UART Module Initializations and Configurations
- 8.5.6 Build an Example UART Module Project
- 8.5.7 The UART API Functions Provided by the TivaWare™ Peripheral Driver Library
- 8.6 Chapter Summary
- Homework
- 9: ARM® Cortex®-M4 Timer and USB Programming
- 9.1 Overview and Introduction
- 9.2 General-Purpose Timers
- 9.2.1 The GPTM Architecture and Functional Block Diagram
- 9.2.2 The General-Purpose Timer Module Components
- 9.2.3 The General-Purpose Timer Module Operational Modes
- 9.2.4 The General-Purpose Timer Module Registers
- 9.2.4.1 Timer A Control Register Group
- 9.2.4.1.1 GPTM Configuration Register (GPTMCFG)
- 9.2.4.1.2 GPTM Control Register (GPTMCTL)
- 9.2.4.1.3 GPTM Timer A Mode Register (GPTMTAMR)
- 9.2.4.1.4 GPTM Timer A Interval Load Register (GPTMTAILR)
- 9.2.4.1.5 GPTM Timer A Match Register (GPTMTAMATCHR)
- 9.2.4.1.6 GPTM Timer A Prescale Register (GPTMTAPR)
- 9.2.4.1.7 GPTM Timer A Prescale Match Register (GPTMTAPMR)
- 9.2.4.1.8 GPTM Timer A Prescale Snapshot Register (GPTMTAPS)
- 9.2.4.2 Timer A Status Register Group
- 9.2.4.3 Timers A and B Interrupt and Configuration Register Group
- 9.2.4.3.1 GPTM Interrupt Mask Register (GPTMIMR)
- 9.2.4.3.2 GPTM Raw Interrupt Status Register (GPTMRIS)
- 9.2.4.3.3 GPTM Masked Interrupt Status Register (GPTMMIS)
- 9.2.4.3.4 GPTM Interrupt Clear Register (GPTMICR)
- 9.2.4.3.5 GPTM Synchronize Register (GPTMSYNC)
- 9.2.4.3.6 GPTM Peripheral Properties Register (GPTMPP)
- 9.2.4.1 Timer A Control Register Group
- 9.2.5 The General-Purpose Timer Module GPIO-Related Control Signals
- 9.2.6 The General-Purpose Timer Module Initializations and Configurations
- 9.2.6.1 Initialization and Configuration for One-Shot/Periodic Timer Mode
- 9.2.6.2 Initialization and Configuration for Input Edge-Count Mode
- 9.2.6.3 Initialization and Configuration for Input Edge-Time Mode
- 9.2.6.4 Initialization and Configuration for Real-Time Clock (RTC) Mode
- 9.2.6.5 Initialization and Configuration for PWM Mode
- 9.2.7 Build an Example General Purpose Timer Project
- 9.2.8 Popular Implementations on GPTM Modules
- 9.2.9 The API Functions Used for General-Purpose Timer Module
- 9.3 Watchdog Timers
- 9.3.1 The Watchdog Timer Architecture and Functional Block Diagram
- 9.3.2 The Watchdog Timer Operational Sequence and Timing Access
- 9.3.3 The Watchdog Timer Registers
- 9.3.4 The Watchdog Timer Module Initializations and Configurations
- 9.3.5 Build an Example Watchdog Timer Project
- 9.3.6 The API Functions Used for Watchdog Timer Modules
- 9.4 Universal Serial Bus (Usb) Controller
- 9.4.1 The Hardware Configuration of the USB Devices
- 9.4.2 The USB Components and Operational Sequence
- 9.4.3 The Serial Interface Protocol of the USB Communications
- 9.4.4 The USB Interface Used in the Embedded System
- 9.4.5 The USB in the TM4C123GH6PM MCU System
- 9.4.6 The USB Registers
- 9.4.7 The USB Initializations and Configurations
- 9.4.8 A USB Implementation Example Project
- 9.4.9 The USB API Functions Provided by the TivaWare™ Peripheral Driver Library
- 9.4.10 Build a USB Implementation Example Project Using the API Functions
- 9.5 Chapter Summary
- Homework
- 10: ARM® Cortex®-M4 Other Peripherals Programming
- 10.1 Overview and Introduction
- 10.2 The Controller Area Network (Can)
- 10.2.1 CAN Standard Frame
- 10.2.2 CAN Extended Frame
- 10.2.3 Detecting and Signaling Errors
- 10.2.4 The CAN Functional Block Diagram in the TM4C123GH6PM System
- 10.2.5 The CAN Components and Operational Procedures
- 10.2.6 The CAN Module Registers
- 10.2.6.1 The CAN Global Control and Status Registers
- 10.2.6.1.1 The CAN Global Control Register (CANCTL)
- 10.2.6.1.2 The CAN Global Status Register (CANSTS)
- 10.2.6.1.3 The CAN Error Counter Register (CANERR)
- 10.2.6.1.4 The CAN Bit Timing Register (CANBIT)
- 10.2.6.1.5 The CAN Test Register (CANTST)
- 10.2.6.1.6 The CAN Baud Rate Prescaler Extension Register (CANBRPE)
- 10.2.6.1.7 The CAN Interrupt Register (CANINT)
- 10.2.6.2 The CAN Interface 1 Registers
- 10.2.6.2.1 CAN IF1 Command Request Register (CANIF1CRQ)
- 10.2.6.2.2 CAN IF1 Command Mask Register (CANIF1CMSK)
- 10.2.6.2.3 CAN IF1 Message Control Register (CANIF1MCTL)
- 10.2.6.2.4 CAN IF1 Mask 1 Register (CANIF1MSK1)
- 10.2.6.2.5 CAN IF1 Mask 2 Register (CANIF1MSK2)
- 10.2.6.2.6 CAN IF1 Arbitration 1 Register (CANIF1ARB1)
- 10.2.6.2.7 CAN IF1 Arbitration 2 Register (CANIF1ARB2)
- 10.2.6.2.8 CAN IF1 Data A1, CAN IF1 Data A2, CAN IF1 Data B1, CAN IF1 Data B2 (CANIF1DA1~CANIF1DA2, CANIF1DB1~CANIF1DB2) Registers
- 10.2.6.3 The CAN Message Object Registers
- 10.2.6.1 The CAN Global Control and Status Registers
- 10.2.7 The CAN Module Interfacing and External Control Signals
- 10.2.8 The CAN API Functions Provided by TivaWare™ Peripheral Driver Library
- 10.2.9 A CAN Module Implementation Example Project
- 10.3 The Quadrature Encoder Interface (Qei)
- 10.3.1 Introduction to Quadrature Encoder
- 10.3.2 The Working Principle of the Increment Rotary Encoder
- 10.3.3 The Increment Rotary Encoder Applied in the Closed-Loop Control System
- 10.3.4 The Increment Rotary Encoder Applied in the TM4C123GH6PM MCU System
- 10.3.5 The QEI Module Registers
- 10.3.6 The QEI Interfacing Signals and Related GPIO Pins
- 10.3.7 The QEI Initialization and Configuration Process
- 10.3.8 QEI API Functions Provided by the TivaWare™ Peripheral Driver Library
- 10.3.9 An Implementation of Using Rotary Encoder for a Closed-Loop Control System
- 10.4 The Continuous and Discrete Pid Closed-Loop Control System
- 10.5 The Fuzzy Logic Closed-Loop Control System
- 10.6 The Analog Comparators
- 10.6.1 The Analog Comparator Architecture and Functional Block Diagram
- 10.6.2 The Control Registers Used in the Analog Comparator Modules
- 10.6.3 The Voltage Reference Registers Used in the Analog Comparator Modules
- 10.6.4 The Interrupt Processing Registers Used in the Analog Comparator Modules
- 10.6.5 The Input and Output Control Signals Used in the Analog Comparators
- 10.6.6 The Initialization and Configuration Process for the Analog Comparator
- 10.6.7 Build a Project to Test the Functions of the Analog Comparator Module
- 10.6.8 Set Up the Environments to Build and Run the Project
- 10.7 Chapter Summary
- Homework
- 11: ARM® Floating Point Unit (FPU)
- 12: ARM® Memory Protection Unit (MPU)
- 12.1 Overview and Introduction
- 12.2 Implementation of the Mpu
- 12.3 Initialization and Configuration of the Mpu
- 12.4 Building a Practical Example Mpu Project
- 12.5 The Api Functions Provided By the Tivaware™ Peripheral Driver Library
- 12.6 Chapter Summary
- Homework
- Index
- About the Author
- End User License Agreement