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Traffic-aware buffer reconfiguration in on-chip networks
- Main Entry: Bashizade, R.
- Title:Traffic-aware buffer reconfiguration in on-chip networks.
- Publisher:IEEE Computer Society, 2015.
- Abstract:Networks-on-Chip (NoCs) play a crucial role in the performance of Chip Multi-Processors (CMPs). Routers are one of the main components determining the efficiency of NoCs. As various applications have different communication characteristics and hence, buffering requirements, it is difficult to make proper decisions in this regard in the design time. In this paper, we propose a traffic-aware reconfigurable router which can adapt its buffers structure to the changes in the traffic of the network. Our proposed router manages to achieve up to 18.8% and 44.4% improvements in terms of postponing saturation rate under synthetic traffic patterns, and average packet latency for PARSEC applications, respectively, with respect to the conventional state-of-the-art router
- Notes:Sharif Repository
- Subject:Reconfigurable hardware.
- Subject:Average packet latencies.
- Subject:Buffering requirements.
- Subject:Chip multi-processors (CMPs)
- Subject:Networks on chips.
- Subject:On-chip networks.
- Subject:State of the art.
- Subject:Traffic pattern.
- Subject:Programmable logic controllers.
- Added Entry:Sarbazi-Azad, H.
- Added Entry:Sharif University of Technology.
- Added Entry:23rd IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, 5 October 2015 through 7 October 2015
- Added Entry: VLSI-SoC 2015
- Source: IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC, 5 October 2015 through 7 October 2015 ; Volume 2015-October , 2015 , Pages 201-206 ; 23248432 (ISSN) ; 9781467391405 (ISBN)
- Web Site:http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7314416