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An efficient reconfigurable architecture by characterizing most frequent logic functions
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An efficient reconfigurable architecture by characterizing most frequent logic functions

Ahmadpour, I.

  1. DOI:10.1109/FPL.2015.7293953
  2. Main Entry: Ahmadpour, I.
  3. Title:An efficient reconfigurable architecture by characterizing most frequent logic functions.
  4. Publisher:Institute of Electrical and Electronics Engineers Inc, 2015.
  5. Abstract:Generous flexibility of Look-Up Tables (LUTs) in implementing arbitrary functions comes with significant performance and area overheads compared with their Application-Specific Integrated Circuit (ASIC) equivalent. One approach to alleviate such overheads is to use less flexible logic elements capable to implement majority of logic functions. In this paper, we first investigate the most frequently used functions in standard benchmarks and then design a set of less-flexible but area-efficient logic cells, called Hard Logics (HL). Since higher input functions have diverse classes, we leverage Shannon decomposition to break them into smaller ones to either reduce the HL design space complexity or attain asymmetric low input functions. A heterogeneous LUT-HL architecture and a mapping scheme are also proposed to attain maximum logic resource usage. Experimental results on MCNC benchmarks demonstrate that the proposed architecture reduces area-delay product by 13% and 36% as compared to LUT4 and LUT6 based FPGAS, respectively. Considering the same area budget, our proposed architecture improves performance by 17% and 2% as compared to LUT4 and LUT6 based FPGAS
  6. Notes:Sharif Repository
  7. Subject:Application specific integrated circuits.
  8. Subject:Budget control.
  9. Subject:Field programmable gate arrays (FPGA)
  10. Subject:Integrated circuit design.
  11. Subject:Logic devices.
  12. Subject:Reconfigurable architectures.
  13. Subject:Reconfigurable hardware.
  14. Subject:Table lookup.
  15. Subject:Arbitrary functions.
  16. Subject:Area-Efficient.
  17. Subject:Input functions.
  18. Subject:Logic elements.
  19. Subject:Logic functions.
  20. Subject:Logic resources.
  21. Subject:Proposed architectures.
  22. Subject:Shannon decomposition.
  23. Subject:Computer circuits.
  24. Added Entry:Khaleghi, B.
  25. Added Entry:Asadi, H.
  26. Added Entry:Sharif University of Technology.
  27. Added Entry:25th International Conference on Field Programmable Logic and Applications, FPL 2015, London; United Kingdom ,2 September 2015 through 4 September 2015
  28. Source: 25th International Conference on Field Programmable Logic and Applications, FPL 2015, 2 September 2015 through 4 September 2015 ; Sept , 2015 , Page(s): 1 - 6 ; 9780993428005 (ISBN)
  29. Web Site:http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7293953

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