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PEAF: A power-efficient architecture for SRAM-based fpgas using reconfigurable hard logic design in dark silicon era
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PEAF: A power-efficient architecture for SRAM-based fpgas using reconfigurable hard logic design in dark silicon era

Ebrahimi, Z.

  1. DOI:10.1109/TC.2016.2636141
  2. Main Entry: Ebrahimi, Z.
  3. Title:PEAF: A power-efficient architecture for SRAM-based fpgas using reconfigurable hard logic design in dark silicon era.
  4. Publisher:IEEE Computer Society, 2017.
  5. Abstract:Significant increase of static power in nano-CMOS era and, subsequently, the end of Dennard scaling has put a Power Wall to further integration of CMOS technology in Field-Programmable Gate Arrays (FPGAs). An efficient solution to cope with this obstacle is power gating inactive fractions of a single die, resulting in Dark Silicon. Previous studies employing power gating on SRAM-based FPGAs have primarily focused on using large-input Look-up Tables (LUTs). The architectures proposed in such studies inherently suffer from poor logic utilization which limits the benefits of power gating techniques. This paper proposes a Power-Efficient Architecture for FPGAs (PEAF) based on combination of Reconfigurable Hard Logics (RHLs) and a small-input LUT. In the proposed architecture, we selectively turn off unused RHLs and/or LUTs within each logic block by employing a reconfigurable controller. By mapping a majority of logic functions to simple-design RHLs, PEAF is able to significantly improve power efficiency without deteriorating the performance. Experimental results over a comprehensive set of benchmarks (MCNC, IWLS'05, and VTR) demonstrate that compared with baseline four-LUT architecture, PEAF reduces the total static power and Power-Delay-Product (PDP), on average, by 24.5 and 21.7 percent, respectively. This is while the overall system performance is also improved by 1.8 percent. PEAF increases total area by 18.9 percent, however, it still occupies 22.1 percent less area footprint than the six-LUT architecture with 31.5 percent improvement in PDP. © 2017 IEEE
  6. Notes:Sharif Repository
  7. Subject:dark silicon.
  8. Subject:Field-programmable gate arrays.
  9. Subject:hard logic.
  10. Subject:SRAM.
  11. Subject:static power.
  12. Subject:Architecture.
  13. Subject:CMOS integrated circuits.
  14. Subject:Computer circuits.
  15. Subject:Field programmable gate arrays (FPGA)
  16. Subject:Integrated circuit design.
  17. Subject:Logic gates.
  18. Subject:Reconfigurable architectures.
  19. Subject:Silicon.
  20. Subject:Static random access storage.
  21. Subject:Table lookup.
  22. Subject:CMOS technology.
  23. Subject:Dark silicons.
  24. Subject:hard logic.
  25. Subject:Power delay product.
  26. Subject:Power efficiency.
  27. Subject:Proposed architectures.
  28. Subject:Reconfigurable controllers.
  29. Subject:Static power.
  30. Subject:Reconfigurable hardware.
  31. Added Entry:Khaleghi, B.
  32. Added Entry:Asadi, H.
  33. Added Entry:Sharif University of Technology.
  34. Source: IEEE Transactions on Computers ; Volume 66, Issue 6 , 2017 , Pages 982-995 ; 00189340 (ISSN)
  35. Web Site:https://ieeexplore.ieee.org/document/7775010

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