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Sequential equivalence checking using a hybrid boolean-word level decision diagram
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Sequential equivalence checking using a hybrid boolean-word level decision diagram

Alizadeh, B.

  1. DOI:10.1007/978-3-540-89985-3_85
  2. Main Entry: Alizadeh, B.
  3. Title:Sequential equivalence checking using a hybrid boolean-word level decision diagram.
  4. Publisher:2008.
  5. Abstract:By increasing the complexity of system on a chip (SoC) formal equivalence checking has become more and more important and a major economical issue to detect design faults at early stages of the design cycle in order to reduce time-to-market as much as possible. However, lower level methods such as BDDs and SAT solvers suffer from memory and computational explosion problems to match sizes of industrial designs in formal equivalence verification. In this paper, we describe a hybrid bit- and word-level canonical representation called Linear Taylor Expansion Diagram (LTED) [1] which can be used to check the equivalence between two descriptions in different levels of abstractions. To prove the validity of our approach, it is run on some industrial circuits with application to communication systems and experimental results are compared to those of Taylor Expansion Diagram (TED) which is also a word level canonical representation [2]. © 2008 Springer-Verlag
  6. Notes:Sharif Repository
  7. Subject:Canonical representations.
  8. Subject:Design cycle.
  9. Subject:Design faults.
  10. Subject:Equivalence checking.
  11. Subject:Formal equivalence verification.
  12. Subject:Formal verifications.
  13. Subject:Industrial circuits.
  14. Subject:Industrial design.
  15. Subject:Level method.
  16. Subject:Levels of abstraction.
  17. Subject:SAT solvers.
  18. Subject:Sequential equivalence checking.
  19. Subject:System on a chip.
  20. Subject:System on chips.
  21. Subject:Taylor expansion diagrams.
  22. Subject:Time-to-market.
  23. Subject:Word level.
  24. Subject:Word-level decision diagrams.
  25. Subject:Communication systems.
  26. Subject:Computer science.
  27. Subject:Decision theory.
  28. Subject:Design.
  29. Subject:Programmable logic controllers.
  30. Subject:Sequential circuits.
  31. Subject:Equivalence classes.
  32. Added Entry:Fujita, M.
  33. Added Entry:Sharif University of Technology.
  34. Added Entry:Communications in Computer and Information Science, 9 March 2008 through 11 March 2008, Kish Island
  35. Source: 13th International Computer Society of Iran Computer Conference on Advances in Computer Science and Engineering, CSICC 2008, Kish Island, 9 March 2008 through 11 March 2008 ; Volume 6 CCIS , 2008 , Pages 697-704 ; 18650929 (ISSN); 3540899847 (ISBN); 9783540899846 (ISBN)
  36. Web Site:https://link.springer.com/chapter/10.1007/978-3-540-89985-3_85

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