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An FPGA based implementation of G.729
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An FPGA based implementation of G.729

Mobini, N.

  1. DOI:10.1109/ISCAS.2005.1465401
  2. Main Entry: Mobini, N.
  3. Title:An FPGA based implementation of G.729.
  4. Publisher:2005.
  5. Abstract:Main objective of this article is to present the implementation and simulation of a Conjugate Structure Algebraic Code Excited Linear Prediction speech coder (CSACELP) based upon ITU-T's G.729 recommendation and to optimize it for real-time implementation on an FPGA. The suggested architecture is characterized by pipelining and parallel operation of functional units; using fixed point two's complement representation for integers. The design was functionally verified by utilizing the ModelSim software package from Mentor Graphics Corporation Company and then synthesized by Xilinx Integrated Software Environment (ISE) 6.1 software. Preliminary results show that the overall system delay is less than 2 ms for each frame. © 2005 IEEE
  6. Notes:Sharif Repository
  7. Subject:Algebraic code-excited linear prediction.
  8. Subject:Conjugate structures.
  9. Subject:CS-ACELP.
  10. Subject:Fixed points.
  11. Subject:FPGA-based implementation.
  12. Subject:Functional units.
  13. Subject:Integrated software environments.
  14. Subject:Mentor Graphics.
  15. Subject:Modelsim software.
  16. Subject:Parallel operations.
  17. Subject:Real-time implementations.
  18. Subject:Speech coders.
  19. Subject:System delay.
  20. Subject:Field programmable gate arrays (FPGA)
  21. Subject:Real time control.
  22. Subject:Computer software.
  23. Added Entry:Vahdat, B.
  24. Added Entry:Radfar, M. H.
  25. Added Entry:Sharif University of Technology.
  26. Source: IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005, Kobe, 23 May 2005 through 26 May 2005 ; 2005 , Pages 3571-3574 ; 02714310 (ISSN)
  27. Web Site:https://ieeexplore.ieee.org/document/1465401

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